Instructions and logic to provide general purpose GF(256) SIMD cryptographic arithmetic functionality

Patent metadata

Field	Value
Publication number	US-9906359-B2
Application number	US-201715405898-A
Country	US
Kind code	B2
Filing date	Jan 13, 2017
Priority date	Dec 28, 2007
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

Instructions and logic provide general purpose GF(2 8 ) SIMD cryptographic arithmetic functionality. Embodiments include a processor to decode an instruction for a SIMD affine transformation specifying a source data operand, a transformation matrix operand, and a translation vector. The transformation matrix is applied to each element of the source data operand, and the translation vector is applied to each of the transformed elements. A result of the instruction is stored in a SIMD destination register. Some embodiments also decode an instruction for a SIMD binary finite field multiplicative inverse to compute an inverse in a binary finite field modulo an irreducible polynomial for each element of the source data operand. Some embodiments also decode an instruction for a SIMD binary finite field multiplication specifying first and second source data operands to multiply each corresponding pair of elements of the first and second source data operand modulo an irreducible polynomial.

First claim

What is claimed is:

1. A processor comprising:
a decode stage to decode a first instruction for a Single Instruction Multiple Data (SIMD) binary finite field multiplicative inverse to generate a first micro-instruction and a second micro-instruction, the first instruction specifying a source data operand set, and a monic irreducible polynomial; and
one or more execution units, responsive to the decoded first instruction, to:
compute a binary finite-field multiplicative inverse element for each element of the source data operand set according to the first micro-instruction;
reduce the binary finite-field multiplicative inverse element of each element of the source data operand set modulo the irreducible polynomial according to the second micro-instruction; and
store a result of the first instruction in a SIMD destination register.

2. The processor of claim 1 , wherein the first instruction specifies said SIMD destination register as a destination operand.

3. The processor of claim 1 , wherein the first instruction specifies a SIMD register to hold 16 byte elements as the source data operand set.

4. The processor of claim 1 , wherein the first instruction specifies a SIMD register to hold 32 byte elements as the source data operand set.

5. The processor of claim 1 , wherein the first instruction specifies a SIMD register to hold 64 byte elements as the source data operand set.

6. The processor of claim 1 , wherein computing the SIMD binary finite field multiplicative inverse is performed by raising each element of the source data operand set to the power 254 modulo the irreducible polynomial in the Galois field GF(28).

7. The processor of claim 1 , wherein the irreducible polynomial is specified in the first instruction mnemonic as 1B to indicate x8+x4+x3+x+1 in the Galois field GF(28).

8. The processor of claim 1 , wherein the irreducible polynomial is specified in an immediate operand of the first instruction as a hexadecimal control value 1B to indicate x8+x4+x3+x+1 in the Galois field GF(28).

9. The processor of claim 1 , wherein the irreducible polynomial is specified in an immediate operand of the first instruction as a hexadecimal control value F5 to indicate x8+x7+x6+x5+x4+x2+1 in the Galois field GF(28).

10. A method comprising:
decoding a first instruction for a Single Instruction Multiple Data (SIMD) binary finite field multiplicative inverse to generate a first micro-instruction and a second micro-instruction, the first instruction specifying a source data operand set, and a monic irreducible polynomial;
computing a binary finite-field multiplicative inverse element for each element of the source data operand set according to the first micro-instruction;
reducing the binary finite-field multiplicative inverse element of each element of the source data operand set modulo the irreducible polynomial according to the second micro-instruction; and
storing a result of the first instruction in a SIMD destination register.

11. The method of claim 10 , wherein the monic irreducible polynomial is specified in an immediate operand of the first instruction as a hexadecimal control value 1B to indicate x8+x4+x3+x+1 in the Galois field GF(28).

12. The method of claim 10 , wherein the irreducible polynomial is specified in the first instruction mnemonic as 1B to indicate x8+x4+x3+x+1 in the Galois field GF(28).

13. The method of claim 10 , wherein the first instruction specifies said SIMD destination register as a destination operand.

14. The method of claim 10 , wherein the first instruction specifies a SIMD register to hold 16 byte elements as the source data operand set.

15. The method of claim 10 , wherein the first instruction specifies a SIMD register to hold 32 byte elements as the source data operand set.

16. The method of claim 10 , wherein the first instruction specifies a SIMD register to hold 64 byte elements as the source data operand set.

17. The method of claim 10 , wherein computing the SIMD binary finite field multiplicative inverse is performed by raising each element of the source data operand set to the power 254 modulo the irreducible polynomial in the Galois field GF(28).

18. A processing system comprising:
a memory to store micro-instructions; and
a processor, operatively coupled to the memory, to:
decode a first instruction for a Single Instruction Multiple Data (SIMD) binary finite field multiplicative inverse to generate a first micro-instruction and a second micro-instruction, the first instruction specifying a source data operand set, and a monic irreducible polynomial;
compute a binary finite-field multiplicative inverse element for each element of the source data operand set according to the first micro-instruction;
reduce the binary finite-field multiplicative inverse element of each element of the source data operand set modulo the irreducible polynomial according to the second micro-instruction; and
store a result of the first instruction in a SIMD destination register.

19. The processing system of claim 18 , wherein the first instruction specifies said SIMD destination register as a destination operand.

20. The processing system of claim 18 , wherein the first instruction specifies a SIMD register to hold 16 byte elements as the source data operand set.

21. The processing system of claim 18 , wherein the first instruction specifies a SIMD register to hold 32 byte elements as the source data operand set.

22. The processing system of claim 18 , wherein the first instruction specifies a SIMD register to hold 64 byte elements as the source data operand set.

23. The processing system of claim 18 , wherein computing the SIMD binary finite field multiplicative inverse is performed by raising each element of the source data operand set to the power 254 modulo the irreducible polynomial in the Galois field GF(28).

24. The processing system of claim 18 , wherein the irreducible polynomial is specified in the first instruction mnemonic as 1B to indicate x8+x4+x3+x+1 in the Galois field GF(28).

25. The processing system of claim 18 , wherein the irreducible polynomial is specified in an immediate operand of the first instruction as a hexadecimal control value 1B to indicate x8+x4+x3+x+1 in the Galois field GF(28).

26. The processing system of claim 18 , wherein the irreducible polynomial is specified in an immediate operand of the first instruction as a hexadecimal control value F5 to indicate x8+x7+x6+x5+x4+x2+1 in the Galois field GF(28).

Assignees

• Intel Corp

Inventors

• Gueron Shay

Classifications

• G06F7/00 Primary

  Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K19/00) · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• H04L9/0631 Primary

  Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms · CPC title

• G06F9/30007

  to perform operations on data operands · CPC title

• G06F21/602

  Providing cryptographic facilities or services · CPC title