On-die signal measurement circuit and method

Patent metadata

Field	Value
Publication number	US-9906355-B2
Application number	US-201314758973-A
Country	US
Kind code	B2
Filing date	Jan 9, 2013
Priority date	Jan 9, 2013
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

There is provided a method, apparatus and integrated circuit for measuring a signal, the apparatus comprising a plurality of sample stages arranged in series, each sample stage comprising a delay element, and a sample element, wherein an input of the sample element is coupled to an output of the delay element, and a strobe line for controlling a sample time of the sample elements, the strobe line comprising a plurality of strobe delay elements arranged in series, wherein an output of each strobe delay element is coupled to one or more sample elements.

First claim

The invention claimed is:

1. An integrated circuit comprising a test circuit for sampling a signal on the integrated circuit, the test circuit comprising:
a plurality of sample stages arranged in series, each sample stage comprising a delay element, and
a sample element, wherein an input of the sample element is coupled to an output of the delay element; and

a strobe line for controlling a sample time of the sample elements, wherein the strobe line comprises a plurality of strobe delay elements arranged in series, and an output of each strobe delay element is coupled to one or more sample elements, wherein a delay time of each of the delay elements is equal to a delay time of each of the strobe delay elements.

2. The integrated circuit of claim 1 wherein the output of the delay element of one sample stage is coupled to an input of the delay element of a subsequent sample stage.

3. The integrated circuit of claim 1 , wherein a direction of increasing delay of the plurality of sample stages is opposite to a direction of increasing delay of the strobe line.

4. An integrated circuit comprising a test circuit for sampling a signal on the integrated circuit, the test circuit comprising:
a plurality of sample stages arranged in series, each sample stage comprising a delay element, and
a sample element, wherein an input of the sample element is coupled to an output of the delay element; and

a strobe line for controlling a sample time of the sample elements, wherein the strobe line comprises a plurality of strobe delay elements arranged in series, and an output of each strobe delay element is coupled to one or more sample elements, wherein the output of each strobe delay element is coupled to a single sample element.

5. The integrated circuit of claim 1 , wherein a delay time of each of the delay elements is not equal to a delay time of each of the strobe delay elements.

6. A method of sampling a signal, the method comprising:
inputting the signal to a delay line comprising a plurality of delay elements; and
sampling an output of each of the plurality of delay elements using a respective sample element, wherein a sample time of a first group of one or more sample elements is delayed relative to a sample time of a neighbouring group of one or more sample elements, wherein a delay time of each of the delay elements is equal to the delay in sample time between neighbouring groups of sample elements.

7. The method of claim 6 , wherein
the sample time of the sample element is controlled by a strobe signal carried by a strobe line;
the strobe line comprises a plurality of strobe delay elements arranged in series; and
an output of each strobe delay element is coupled to a group of one or more sample elements.

8. The method of claim 6 wherein the sample of time of the first group is delayed relative to a subsequent group of one or more delay elements in the delay line.

9. The method of claim 6 , further comprising calibrating a delay time of the plurality of delay elements by configuring the delay line as a ring oscillator.

10. The method of claim 9 , further comprising calibrating the delay in sample time between neighbouring groups of sample elements based on a calibrated delay time of the plurality of delay elements.

11. The method of claim 6 further comprising calculating a pulse width associated with the signal based on the sampled output of each of the plurality of delay elements.

12. The integrated circuit of claim 4 wherein the output of the delay element of one sample stage is coupled to an input of the delay element of a subsequent sample stage.

13. The integrated circuit of claim 4 , wherein a direction of increasing delay of the plurality of sample stages is opposite to a direction of increasing delay of the strobe line.

14. The integrated circuit of claim 4 , wherein a delay time of each of the delay elements is not equal to a delay time of each of the strobe delay elements.

Assignees

• Priel Michael
• Fleshel Leonid
• Mostinski Roman
• Nusimovich Vladimir
• Nxp Usa Inc

Inventors

• Priel Michael
• Fleshel Leonid
• Mostinski Roman
• Nusimovich Vladimir

Classifications

• G01R31/2837 Primary

  Characterising or performance testing, e.g. of frequency response (transient response G01R27/28) · CPC title

• G01R31/31712

  Input or output aspects · CPC title

• G11C19/00

  Digital stores in which the information is moved stepwise, e.g. shift registers · CPC title

• H04L7/00 Primary

  Arrangements for synchronising receiver with transmitter {(synchronisation of generators of electric oscillations or pulses H03L7/00)} · CPC title

• G01R31/2884

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title