Superconducting multi-bit digital mixer

Patent metadata

Field	Value
Publication number	US-9906191-B1
Application number	US-201615052379-A
Country	US
Kind code	B1
Filing date	Feb 24, 2016
Priority date	Aug 2, 2010
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A superconducting multi-bit digital mixer, designed using rapid single flux quantum (RSFQ) logic, for multiplying two independent digital streams, at least one of these comprising a plurality of parallel bit lines, wherein the output is also a similar plurality of bit lines. In a preferred embodiment, one of the digital streams represents a local oscillator signal, and the other digital stream digital radio frequency input from an analog-to-digital converter. The multi-bit mixer comprises an array of bit-slices, with the local oscillator signal generated using shift registers. This multi-bit mixer is suitable for an integrated circuit with application to a broadband digital radio frequency receiver, a digital correlation receiver, or a digital radio frequency transmitter. A synchronous pulse distribution network is used to ensure proper operation at data rates of 20 GHz or above.

First claim

What is claimed is:

1. A multibit digital mixer constructed employing pulse logic, comprising:
a first pulse input port configured to receive at least one first digital input signal pulse;
a second pulse input port configured to receive at least one second digital input signal pulse;
at least one of the first and second digital input signal pulses comprising a plurality of pulses;
a multiplier circuit configured to generate a multiplication product of the at least one first digital input signal pulse and the at least one second digital input signal pulse, as a multibit set of digital output signal pulses; and
a pulse output port configured to transmit the multibit set of digital output signal pulses.

2. The multibit digital mixer of claim 1 , wherein at least one of the at least one first digital input signal pulse and the at least one second digital input signal pulse is received from a respective shift register.

3. The multibit digital mixer of claim 1 , wherein the at least one first digital input signal pulse is communicated over at least one matched pair of complementary signal lines as a pair of corresponding binary inputs.

4. The multibit digital mixer of claim 1 , wherein the pulse output port is configured to transmit the multibit set of digital output signal pulses as a set of parallel bit pulses, and the multiplier circuit comprises a plurality of bit slices, having a corresponding bit slice for each respective parallel bit pulse of the multibit set of digital output signal pulses.

5. The multibit digital mixer of claim 4 , wherein each bit slice comprises at least one respective XOR-based pulse logic mixer cell.

6. The multibit digital mixer of claim 1 , wherein at least one of the at least one first digital input signal pulse and the at least one second digital input signal pulse is received through a synchronous pulse distribution network (SPDN) configured to ensure proper multibit timing.

7. The multibit digital mixer of claim 6 , wherein the circuit comprises at least one asynchronous RSFQ mixer.

8. The multibit digital mixer of claim 1 , wherein the multiplier circuit comprises at least one Josephson junction.

9. The multibit digital mixer of claim 1 , wherein the at least one first digital input signal pulse and the at least one second digital input signal pulse have respectively different clock rates.

10. The multibit digital mixer of claim 1 , wherein the at least one first digital input signal pulse is generated by a multibit analog to digital converter and the at least one second digital input signal pulse is generated by at least one of a digital local oscillator and a code generator.

11. The multibit digital mixer of claim 10 , wherein the multibit analog to digital converter receives a modulated radio frequency signal, and the multiplier circuit is configured to mix the modulated radio frequency signal with the at least one second digital input signal pulse to generate the multibit set of digital output signal pulses representing at least a difference frequency.

12. The multibit digital mixer of claim 1 , wherein the multiplier circuit is configured to generate the multibit set of digital output signal pulses without a representation of a carry.

13. The multibit digital mixer of claim 1 , wherein the multibit set of digital output signal pulses represents a frequency down-conversion of a radio frequency receiver output having a carrier frequency of at least 250 MHz, and the at least one first digital input signal pulse is received from a multibit analog to digital converter having a sampling rate of at least 1 GHz.

14. The multibit digital mixer of claim 1 , configured in a multiphase radio receiver for receiving a plurality of phases, comprising:
a plurality of multibit digital mixers according to claim 1 , at least one provided for each respective one of the plurality of phases;
a plurality of multibit analog to digital converters, each operating at a digital sample rate of at least 1.5 GHz, for each respective one of the plurality of phases, each generating a respective at least one first digital input signal pulse; and
a plurality of code generators, each code generator comprising at least one local oscillator and at least one shift register.

15. A multibit digital mixing method, comprising:
receiving at least one first digital input signal pulse;
receiving at least one second digital input signal pulse;
at least one of the first digital input signal pulse and the second digital input signal pulse comprising a plurality of pulses;
generating a multiplication product of the at least one first digital input signal pulse and the at least one second digital input signal pulse, with a multibit multiplier circuit operating without a carry operation, the multiplication product being a multibit set of digital output signal pulses; and
transmitting the multibit set of digital output signal pulses.

16. The method according to claim 15 ,
wherein each of the at least one first digital input signal pulse, at least one second digital input signal pulse, and multibit set of digital output signal pulses comprise rapid single quantum flux (RSFQ) signals, wherein each signal bit is represented as complementary signal pairs;
further comprising ensuring proper timing of the at least one first digital input signal pulse, at least one second digital input signal pulse with a synchronous pulse distribution network (SPDN); and
the multiplier circuit comprises an array of XOR-based asynchronous mixer cells, at least one for each bit line of the multibit set of digital output signal pulses.

17. The method of claim 15 , for implementing a multiphase radio receiver for receiving a plurality of phases, comprising:
providing a plurality of multibit multiplier circuits, at least one provided for each respective one of the plurality of phases;
receiving a plurality of the at least one first digital input signal pulses from a plurality of multibit analog to digital converters, each operating at a digital sample rate of at least 1.5 GHz, at least one multibit analog to digital converter being provided for each respective one of the plurality of phases, each generating a respective multibit first digital input signal pulse; and
receiving a plurality of the at least one second digital input signal pulses from a plurality of code generators, at least one code generator being provided for each respective multibit multiplier circuit, each code generator comprising at least one local oscillator and at least one shift register.

18. A multibit digital mixer, comprising:
a first input port configured to receive a plurality of pulse logic first digital input signal pulses;
a second input port configured to receive at least one pulse logic second digital input signal pulse;
the a plurality of pulse logic first digital input signal pulses and the at least one pulse logic second digital input signal pulse being asynchronous;
a synchronous pulse distribution network configured to synchronize timing of the plurality of pulse logic first digital input signal pulses with the at least one pulse logic second digital input signal pulse;
a pulse logic multiplier circuit configured to generate a multiplication product of the synchronized plurality of pulse logic first digital input signal pulses and the at least one pulse logic second digital input signal pulse, as a pulse logic multibit digital output signal.

19. The multibit digital mixer of claim 18 , wherein the multiplier circuit comprises a respective bit slice for each respective b

Assignees

• Hypres Inc

Inventors

• Filippov Timur V
• Kirichenko Alexander F
• Gupta Deepnarayan

Classifications

• H01L39/025

  Electricity · mapped topic

• H03D7/005 Primary

  by means of superconductive devices · CPC title

• H04B1/0014 Primary

  using DSP [Digital Signal Processor] quadrature modulation and demodulation · CPC title

• H10N60/805

  for Josephson-effect devices · CPC title

• H10N60/12

  Josephson-effect devices · CPC title