Zero-voltage switch-mode power converter

Patent metadata

Field	Value
Publication number	US-9906131-B1
Application number	US-201615243022-A
Country	US
Kind code	B1
Filing date	Aug 22, 2016
Priority date	Aug 22, 2016
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.

First claim

What is claimed is:

1. A switch-mode power converter comprising:
a bridge node having a bridge voltage;
a first switch having a first input and a first output, the first input having a power converter input voltage, the first output electrically connected to the bridge node, the first switch having a closed state in which the first input is electrically connected to the first output and an open state in which the first input is not electrically connected to the first output;
a second switch having a second input and a second output, the second input electrically connected to the bridge node, the second output electrically connected to a second voltage, the second voltage lower than the power converter input voltage, the second switch having a closed state in which the second input is electrically connected to the second output and an open state in which the second input is not electrically connected to the second output;
a logic circuit in electrical communication with the first and second switches, the logic circuit controlling a respective state of the first and second switches such that the first switch is in the open state when the second switch is in the closed state and the second switch is in the open state when the first switch is in the closed state;
an LC circuit in electrical communication with the bridge node and a power converter load, the power converter load receiving an output current at a power converter output voltage, the power converter output voltage lower than the power converter input voltage;
a PWM and frequency control circuit configured to control (a) a ratio of times that the first and second switches are in respective closed states to control the power converter output voltage and (b) a switching frequency of the first and second switches;
a first delay feedback circuit configured to control a low-to-high delay time between an open time of said second switch and a close time of said first switch; and
a second delay feedback circuit configured to control a high-to-low delay time between an open time of said first switch and a close time of said second switch;
wherein the first and second delay feedback circuits each include a sample and hold circuit and a variable delay circuit; and
wherein the sample and hold circuit of the first delay feedback circuit (a) samples a first switch voltage across the first switch at the close time of the first switch and (b) determines an error between the sampled first switch voltage and the power converter input voltage.

2. The power converter of claim 1 , wherein the first and second switches comprise transistors.

3. The power converter of claim 2 , wherein the first switch comprises a PFET and the second switch comprises an NFET.

4. The power converter of claim 1 , wherein the high-to-low-delay time is selected so that the bridge voltage is equal to the second voltage when the second switch transitions to the closed state.

5. The power converter of claim 1 , wherein the low-to-high-delay time is selected so that the bridge voltage is equal to the power converter input voltage when the first switch transitions to the closed state.

6. The power converter of claim 1 , wherein the variable delay circuit increases the low-to-high-delay time if the sampled first switch voltage is lower than the power converter input voltage.

7. The power converter of claim 1 , wherein the variable delay circuit decreases the low-to-high-delay time if the sampled first switch voltage is higher than the power converter input voltage.

8. The power converter of claim 1 , wherein the sample and hold circuit of the second delay feedback circuit (a) samples a second switch voltage across the second switch at the close time of the second switch and (b) determines an error between the second switch voltage and the second input voltage.

9. The power converter of claim 1 , wherein the variable delay circuit decreases the high-to-low-delay time if the sampled second switch voltage is lower than the second input voltage.

10. The power converter of claim 1 , wherein the variable delay circuit increases the high-to-low-delay time if the sampled first switch voltage is higher than the second input voltage.

11. The power converter of claim 1 , wherein the PWM and frequency control circuit includes a sample and hold circuit in electrical communication with the bridge node and a frequency controller.

12. The power converter of claim 11 , wherein the sample and hold circuit of the PWM and frequency control circuit (a) samples a second open switch voltage across the second switch at the open time of the second switch and (b) determines an error between the second open switch voltage and a reference voltage, the reference voltage selected so that an inductor current of the LC circuit raises the bridge voltage to the power converter input voltage during the low-to-high-delay time.

13. The power converter of claim 12 , wherein the frequency controller decreases the switching frequency of the first and second switches if the second open switch voltage is less than the reference voltage.

14. The power converter of claim 13 , wherein the frequency controller increases the switching frequency of the first and second switches if the second open switch voltage is greater than the reference voltage.

15. The power converter of claim 13 , wherein the frequency controller comprises a voltage controlled oscillator.

16. A method of operating a switch-mode power converter, the method comprising:
controlling a duty cycle of first and second switches electrically connected to a bridge node to convert a power converter input voltage to a power converter output voltage, wherein:
the first switch has a first input and a first output, the first input having a power converter input voltage, the first output electrically connected to a bridge node, the first switch having a closed state in which the first input is electrically connected to the first output and an open state in which the first input is not electrically connected to the first output,
the second switch has a second input and a second output, the second input electrically connected to the bridge node, the second output electrically connected to a second voltage, the second voltage lower than the power converter input voltage, the second switch having a closed state in which the second input is electrically connected to the second output and an open state in which the second input is not electrically connected to the second output, and
first switch is in the open state when the second switch is in the closed state and the second switch is in the open state when the first switch is in the closed state;

discharging the bridge node voltage during a high-to-low-delay time between an open time of the first switch and a close time of the second switch so that the bridge node voltage equals the second voltage at an end of the high-to-low-delay time;
adjusting the high-to-low-delay time if the bridge node voltage does not equal the second voltage at the end of the high-to-low-delay time;
charging the bridge node voltage during a low-to-high-delay time between an open time of the second switch and a close time of the first switch so that the bridge node voltage equals the power converter input voltage at an end of the low-to-high-delay time;
measuring the bridge voltage at the end of the low-to-high-delay time and determining an error between the measured bridge voltage and the power converter input voltage;
adjusting the low-to-high-delay time if the bridge node voltage does not equal the power converter input voltage at the end of the low

Assignees

• Ferric Inc

Inventors

• Lee William
• Jew David
• Meyer Joseph
• Sturcken Noah

Classifications

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M3/1588

  comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence) · CPC title

• H02M3/157

  with digital control · CPC title

• Y02B70/1491

  Cross-Sectional Technologies · mapped topic

• H02M2001/0058

  Electricity · mapped topic