Super-junction structure and method for manufacturing the same and semiconductor device thereof

Patent metadata

Field	Value
Publication number	US-9905636-B2
Application number	US-201514841776-A
Country	US
Kind code	B2
Filing date	Sep 1, 2015
Priority date	Sep 1, 2014
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

The present disclosure relates to a super-junction structure, a method for manufacturing the super-junction structure and a semiconductor device including the super-junction structure. The super-junction structure includes an epitaxy layer of a first doping type and a plurality of first pillar regions of a second doping type which are formed in the epitaxy layer and are separated from each other. Each of the first pillar regions has a doping concentration that decreases from bottom to top. A portion of the epitaxy layer between adjacent ones of the first pillar regions is a second pillar region. The first pillar regions and the second pillar region are arranged alternatively to form the super-junction structure. The first pillar regions are characterized by the doping concentration that decreases from bottom to top so that the super-junction structure has a relatively high breakdown voltage and a relatively low on resistance. Moreover, the super-junction structure changes a path of an avalanche current and thus suppresses an avalanche current so that the device is not easily damaged.

First claim

What is claimed is:

1. A super-junction structure comprising:
an epitaxy layer of a first doping type;
a plurality of first pillar regions of a second doping type, which are formed in said epitaxy layer and separated from each other, and
a second pillar region, which is a portion of said epitaxy layer between adjacent ones of said plurality of first pillar regions and arranged alternatively with said plurality of first pillar regions to form said super-junction structure,
wherein each of said plurality of first pillar regions comprises a first sub-pillar region and a second sub-pillar region, said second sub-pillar region is aligned to and stacked on said first sub-pillar region and has a doping concentration smaller than that of said first sub-pillar region,
when a high voltage is applied to said super-junction structure, a breakdown point is located at said first sub-pillar region, so that an avalanche current flows through said plurality of first pillar regions and said plurality of second pillar regions.

2. The super-junction structure according to claim 1 , wherein said first sub-pillar region has a doping concentration larger that an average doping concentration of said plurality of first pillar regions, and said second sub-pillar region has a doping concentration less than an average doping concentration of said plurality of first pillar regions,
said average doping concentration is a doping concentration of said plurality of first pillar regions in a case that said plurality of first pillar regions have a uniform doping concentration and have a dopant amount equal to that of said second pillar region.

3. The super-junction structure according to claim 1 , wherein said first doping type is an N type and said second doping type is a P type.

4. A semiconductor device, comprising:
a semiconductor substrate;
a super-junction structure according to claim 1 , being arranged above said semiconductor substrate;
well regions of said second doping type, contacting top surfaces of said plurality of first pillar regions and a portion of said top surface of second pillar region;
source regions of said first doping type, being arranged at surfaces of said well regions;
a gate oxide, being arranged above said second pillar region, portions of said well regions and portions of said source regions;
a polysilicon gate, being arranged above said gate oxide;
a front-side metal layer contacting said source regions; and
a back-side metal layer being arranged below and contacts said semiconductor substrate.

5. The semiconductor device according to claim 4 , further comprising an extension portion above said second pillar region, below said gate oxide, and between adjacent ones of said well regions.

6. The semiconductor device according to claim 5 , further comprising contact regions at said surfaces of said well regions, wherein said front-side metal layer contacts said source regions and said contact regions.

7. A semiconductor device, comprising:
a first semiconductor layer;
a super-junction structure according to claim 1 , being arranged above said first semiconductor layer; and
a second semiconductor layer above said super-junction structure,
wherein in a case that said first semiconductor layer is of said first doping type, said second semiconductor layer is of said second doping type, and in a case that said first semiconductor layer is of said second doping type, said second semiconductor layer is of said first doping type.

8. A method for manufacturing a super-junction structure, comprising:
forming an epitaxial layer of a first doping type;
forming a plurality of first sub-pillar regions of a second doping type in said epitaxial layer, wherein said plurality of first sub-pillar regions are separated from each other and have a first doping concentration; and
forming a plurality of second sub-pillar regions of said second doping type on said plurality of first sub-pillar regions in said epitaxial layer, wherein said plurality of second sub-pillar regions have a second doping concentration smaller than said first doping concentration,
wherein each of said plurality of first sub-pillar regions is aligned in a vertical direction to and connected to respective one of said plurality of second sub-pillar regions to form respective one of a plurality of first pillar regions, and
a portion of said epitaxy layer between adjacent ones of said plurality of first pillar regions forms a second pillar region,
when a high voltage is applied to said super-junction structure, a breakdown point is located at said first sub-pillar regions, so that an avalanche current flows through said plurality of first pillar regions and said plurality of second pillar regions.

9. The method according to claim 8 , wherein said first doping concentration is larger than an average doping concentration of said first pillar regions, and said second doping concentration is less than said average doping concentration, and
wherein said average doping concentration is a doping concentration of said plurality of first pillar regions in a case that said plurality of first pillar regions have a uniform doping concentration and said plurality of first pillar region has a dopant amount equal to that of said second pillar region.

10. The method according to claim 9 , wherein forming said epitaxial layer comprises forming a plurality of first sub-epitaxial layers of said first doping type and a plurality of second sub-epitaxial layers of said first doping type, and said plurality of second sub-epitaxial layers are stacked on said plurality of first sub-epitaxial layers.

11. The method according to claim 10 , wherein forming said plurality of first sub-pillar regions comprises doping said plurality of first sub-epitaxial layer with a dopant of a second type to form a plurality of pillar regions which are separated from each other and have said first doping concentration.

12. The method according to claim 10 , wherein forming said plurality of second sub-pillar regions comprises doping said plurality of second sub-epitaxial layer with a dopant of a second type to form a plurality of pillar regions which are separated from each other and have said second doping concentration.

13. The method according to claim 8 , after forming said epitaxial layer and before forming said first sub-pillar regions, further comprising forming a plurality of trenches in said epitaxial layer, so that said second pillar region is located between adjacent ones of said plurality of trenches.

14. The method according to claim 13 , wherein forming said plurality of first sub-pillar regions comprises:
filling lower portions of said plurality of trenches with a first doped layer of said second doping type and having said first doping concentration; and
forming said plurality of second sub-pillar regions comprises:
filling upper portions of said plurality of trenches with a second doped layer of said second doping type and having said second doping concentration.

15. The method according to claim 13 , wherein forming said plurality of first sub-pillar regions comprises:
doping bottoms of said plurality of trenches with a dopant of a second type; and
forming said plurality of second sub-pillar regions comprises:
filling said plurality of trenches with a doped layer of said second doping type and having said second doping concentration.

16. The semiconductor device according to claim 1 , wherein said first sub-pillar region is formed by doping a bottom of a trench in said epitaxy layer with a dopant of said second doping type, and said second sub-p

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Sun He
• Liao Zhongping

Classifications

• H10D62/058

  by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches · CPC title

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D62/111 Primary

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H01L29/7802

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic