Array substrate, display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-9905626-B2
Application number	US-201514802807-A
Country	US
Kind code	B2
Filing date	Jul 17, 2015
Priority date	Dec 8, 2014
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

Embodiments of the present invention provide an array substrate, a display panel and a display apparatus. They relate to the technical field of display technologies and can prevent the peripheral signal wirings of a display region from occupying non-display regions on both sides additionally. In this way, when the array substrate is applied in the display panel, the frame on both sides of the display region on the display panel may be omitted. The array substrate includes: a base substrate; signal lines located in positions on the base substrate corresponding to a display region of the array substrate; a pattern layer, in which the signal lines are arranged; and signal line wirings located between the pattern layer and the base substrate, wherein the signal line wirings are configured to input signals into the signal lines.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
signal lines located in positions on the base substrate corresponding to a display region of the array substrate, wherein the signal lines comprise gate lines;
data lines arranged to cross with the gate lines;
a driving integrated circuit unit located in a first position on the base substrate corresponding to a non-display region of the array substrate and close to a first end of each of the data lines, the driving integrated circuit unit comprising a source driving circuit unit;
a gate driver on array unit located in a second position on the base substrate corresponding to the non-display region of the array substrate and close to a second end of each of the data lines; and
a pattern layer, in which the signal lines are arranged; and
signal line wirings located between the pattern layer and the base substrate and arranged in the display region of the array substrate, wherein the signal line wirings include gate line wirings, and wherein the gate line wirings are configured to input gate scanning signals into the gate lines; and
gate line wiring connection lines arranged in the same layer as the gate line wirings, the gate line wiring connection lines being configured to connect the gate line wirings with the gate driver on array unit; and
gate scanning signal connection lines arranged in the same layer as the gate line wiring connection lines,
wherein the driving integrated circuit unit further comprises a gate driver on array signal unit, the gate scanning signal connection lines being configured to connect the gate driver on array unit with the gate driver on array signal unit, and
wherein the signal line wirings are configured to input signals into the signal lines.

2. The array substrate according to claim 1 , wherein the pattern layer includes a first pattern layer in which the gate lines are arranged, and the array substrate further comprises:
a first insulation layer located between the first pattern layer and the base substrate, the gate line wirings being located between the first insulation layer and the base substrate,
wherein the first insulation layer is provided with first via holes therein, the first via holes being configured to connect the gate lines with the gate line wirings.

3. The array substrate according to claim 1 , wherein the signal lines are composed of metal simple substance and/or metal alloy material, and
wherein the signal line wirings are covered by the signal lines in a direction perpendicular to a plane surface of the base substrate.

4. The array substrate according to claim 1 , wherein the gate line wiring connection lines are composed of metal simple substance and/or metal alloy material, and
wherein the gate line wiring connection lines are parallel to the data lines and the parts of the gate line wiring connection lines overlapped with the data lines are covered by the data lines in a direction perpendicular to a plane surface of the base substrate.

5. The array substrate according to claim 1 , wherein the gate scanning signal connection lines are composed of metal simple substance and/or metal alloy material, and
wherein the parts of the gate scanning signal connection lines overlapped with the data lines are covered by the data lines in a direction perpendicular to a plane surface of the base substrate.

6. The array substrate according to claim 1 , further comprising:
data line leads configured to connect the data lines with the source driving circuit unit.

7. The array substrate according to claim 1 , wherein the signal lines comprise data lines and the signal line wirings comprise data line wirings, and
wherein the data line leads are configured to input source driving signals into the data lines.

8. A display panel comprising an array substrate according to claim 1 .

9. A display apparatus comprising a display panel according to claim 8 .

10. An array substrate, comprising:
a base substrate;
signal lines located in positions on the base substrate corresponding to a display region of the array substrate, wherein the signal lines comprise gate lines;
a pattern layer, in which the signal lines are arranged; and
signal line wirings located between the pattern layer and the base substrate and arranged in the display region of the array substrate, wherein the signal line wirings include gate line wirings, and wherein the gate line wirings are configured to input gate scanning signals into the gate lines;
data lines arranged to cross with the gate lines;
a driving integrated circuit unit located in a position on the base substrate corresponding to a non-display region of the array substrate and close to any end of each of the data lines, the driving integrated circuit unit comprising a gate driving circuit unit and a source driving circuit unit; and
gate line wiring connection lines arranged in the same layer as the gate line wirings, the gate line wiring connection lines being configured to connect the gate line wirings with the gate driving circuit unit,
wherein the signal line wirings are configured to input signals into the signal lines.

11. The array substrate according to claim 10 , wherein the gate line wiring connection lines are composed of metal simple substance and/or metal alloy material, and
wherein the gate line wiring connection lines are parallel to the data lines and the parts of the gate line wiring connection lines overlapped with the data lines are covered by the data lines in a direction perpendicular to a plane surface of the base substrate.

12. The array substrate according to claim 10 , further comprising:
data line leads configured to connect the data lines with the source driving circuit unit.

13. A display panel comprising an array substrate according to claim 10 .

14. A display apparatus comprising a display panel according to claim 13 .

15. An array substrate, comprising:
a base substrate;
signal lines located in positions on the base substrate corresponding to a display region of the array substrate, wherein the signal lines comprise gate lines;
a pattern layer, in which the signal lines are arranged; and
signal line wirings located between the pattern layer and the base substrate and arranged in the display region of the array substrate, wherein the signal line wirings include gate line wirings, and wherein the gate line wirings are configured to input gate scanning signals into the gate lines;
a first insulation layer located between the first pattern layer and the base substrate, the gate line wirings being located between the first insulation layer and the base substrate, wherein the first insulation layer is provided with first via holes therein, the first via holes being configured to connect the gate lines with the gate line wirings;
data lines arranged to cross with the gate lines, the data lines and the gate lines delimiting a plurality of pixel regions;
organic light emitting units arranged in the pixel regions and configured to emit light in a top emitting mode with respect to the base substrate;
a second insulation layer located between the second pattern layer and the base substrate; and
a gate driver on array unit located between the second insulation layer and the base substrate, wherein the second insulation layer is provided with second via holes therein, the second via holes being configured to connect the gate driver on array unit with the gate line wirings,
wherein the signal line wirings are configured to input signals into the signal lines.

16. The array substrate according to claim

Assignees

• Boe Technology Group Co Ltd
• Chongqing Boe Optoelectronnics Tech Co Ltd
• Chongqing Boe Optoelectronics Tech Co Ltd

Inventors

• Wang Rui
• Shang Fei
• Wang Wu
• Li Shaoru

Classifications

• H10W90/00

  Package configurations · CPC title

• H01L2251/5315

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L25/167

  Electricity · mapped topic

• H01L27/3276 Primary

  Electricity · mapped topic