Array substrate comprising a conductive contact formed on a surface of a pixel electrode exposed by an opening, manufacturing method thereof, and display panel

Patent metadata

Field	Value
Publication number	US-9905587-B2
Application number	US-201414500178-A
Country	US
Kind code	B2
Filing date	Sep 29, 2014
Priority date	Mar 7, 2014
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

The present invention provides an array substrate and a manufacturing method thereof, and a display panel comprising said array substrate. The array substrate comprises a plurality of pixel units, each of which comprising: a gate formed on a substrate; a gate insulating layer formed on the gate; an active layer being corresponding to the gate and formed on the gate insulating layer; a source and a drain formed on the active layer respectively; a pixel electrode formed on the gate insulating layer and electrically connected to the drain; a passivation layer covering the source, the drain and the pixel electrode; and a common electrode being corresponding to the pixel electrode and formed on the passivation layer, wherein an opening passing through the passivation layer is formed in the common electrode, so as to expose the pixel electrode below the passivation layer.

First claim

The invention claimed is:

1. An array substrate, comprising a plurality of pixel units, each of which comprises:
a gate formed on a substrate;
a gate insulating layer formed on the gate;
an active layer being corresponding to the gate and formed on the gate insulating layer;
a source and a drain formed on the active layer, respectively;
a pixel electrode formed on the gate insulating layer and electrically connected to the drain;
a passivation layer covering the source, the drain and the pixel electrode;
a common electrode being corresponding to the pixel electrode and formed on the passivation layer, wherein an opening passing through the passivation layer is formed in the common electrode, so as to expose the pixel electrode below the passivation layer; and
a conductive contact formed on a part of the pixel electrode exposed by the opening, wherein the conductive contact is formed only in the opening and is formed on a surface of the pixel electrode away from the gate insulating layer.

2. The array substrate according to claim 1 , wherein the drain is formed on the pixel electrode.

3. A display panel, comprising an array substrate, wherein the array substrate comprises a plurality of pixel units, each of which comprises:
a gate formed on a substrate;
a gate insulating layer formed on the gate;
an active layer being corresponding to the gate and formed on the gate insulating layer;
a source and a drain formed on the active layer, respectively;
a pixel electrode formed on the gate insulating layer and electrically connected to the drain;
a passivation layer covering the source, the drain and the pixel electrode;
a common electrode being corresponding to the pixel electrode and formed on the passivation layer, wherein an opening passing through the passivation layer is formed in the common electrode, so as to expose the pixel electrode below the passivation layer;
a black matrix inside the display panel shields the openings; and
a conductive contact formed on a part of the pixel electrode exposed by the opening, wherein the conductive contact is formed only in the opening and is formed on a surface of the pixel electrode away from the gate insulating layer.

4. The display panel according to claim 3 , wherein the openings are formed in blue pixels of the display panel.

5. The display panel according to claim 3 , wherein the display panel comprises at least nine openings which are distributed uniformly.

6. The display panel according to claim 4 wherein the display panel comprises at least nine openings which are distributed uniformly.

7. A method for manufacturing an array substrate, comprising:
forming a gate on a substrate;
forming a gate insulating layer on the gate;
forming an active layer corresponding to the gate on the gate insulating layer;
forming a pixel electrode on the gate insulating layer;
forming a source and a drain on the active layer;
depositing a passivation layer to cover the source, the drain and the pixel electrode;
forming a common electrode corresponding to the pixel electrode on the passivation layer;
forming an opening passing through the passivation layer in the common electrode, so as to expose the pixel electrode below the passivation layer; and
forming a conductive contact on a part of the pixel electrode exposed by the opening, wherein the conductive contact is formed only in the opening and is formed on a surface of the pixel electrode away from the gate insulating layer.

8. The method according to claim 7 , wherein the conductive contact is formed in the same step as the source and the drain.

9. The method according to any one of claim 7 , wherein the drain is formed on the pixel electrode.

10. The method according to any one of claim 8 , wherein the drain is formed on the pixel electrode.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Ding Jinbo
• Li Bin
• Li Jian
• Ren Jian

Classifications

• H01L29/458

  Electricity · mapped topic

• G02F2001/134372

  Physics · mapped topic

• H01L29/41733

  Electricity · mapped topic

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• H01L29/45

  Electricity · mapped topic