Semiconductor packages and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9905535-B2
Application number	US-201514883592-A
Country	US
Kind code	B2
Filing date	Oct 14, 2015
Priority date	Nov 21, 2014
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A semiconductor package and a method of fabricating the same are provided. The semiconductor package may include a first semiconductor chip with a first circuit pattern, a second semiconductor chip disposed on the first semiconductor chip and provided with a second circuit pattern, and first and second connection structures penetrating the first and second semiconductor chips. The first connection structure may be electrically connected to the first circuit pattern and may be electrically disconnected from the second circuit pattern. The second connection structure may be electrically disconnected from the first circuit pattern and may be electrically connected to the second circuit pattern.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate;
a first semiconductor chip mounted on the substrate and provided with a first circuit pattern;
a second semiconductor chip disposed on the first semiconductor chip and provided with a second circuit pattern;
a first connection structure penetrating the first semiconductor chip and the second semiconductor chip; and
a second connection structure disposed beside the first connection structure to penetrate the first semiconductor chip and the second semiconductor chip,
wherein the first semiconductor chip has the same structure as the second semiconductor chip,
wherein the second semiconductor chip is laterally shifted from the first semiconductor chip in a first direction,
wherein the first connection structure is electrically connected to the first circuit pattern and is electrically disconnected from the second circuit pattern,
wherein the second connection structure is electrically disconnected from the first circuit pattern and is electrically connected to the second circuit pattern,
wherein the first connection structure comprises:
a first connection via provided through the first semiconductor chip and electrically connected to the first circuit pattern; and
a second dummy via provided through the second semiconductor chip and electrically disconnected from the second circuit pattern,

wherein the second dummy via is electrically connected to the first connection via,
wherein the first connection via is overlapped with the second dummy via to form a first column,
wherein the second connection structure comprises:
a first dummy via provided through the first semiconductor chip and electrically disconnected from the first circuit pattern; and
a second connection via provided through the second semiconductor chip electrically connected to the second circuit pattern,

wherein the first dummy via is electrically connected to the second connection via, and
wherein the second connection via is overlapped with the first dummy via to form a second column parallel to the first column.

2. The semiconductor package of claim 1 ,
wherein the first connection structure further comprises:
a first connection terminal provided between the first semiconductor chip and the second semiconductor chip and coupled to the first connection via and the second dummy via.

3. The semiconductor package of claim 2 ,
wherein the second connection structure further comprises:
a second connection terminal provided between the first semiconductor chip and the second semiconductor chip and coupled to the first dummy via and the second connection via.

4. The semiconductor package of claim 1 , further comprising a third semiconductor chip mounted on the second semiconductor chip and provided with a third circuit pattern,
wherein the first connection structure is electrically connected to the third circuit pattern, and
wherein the second connection structure is electrically disconnected from the third circuit pattern.

5. The semiconductor package of claim 1 , further comprising a third semiconductor chip mounted on the second semiconductor chip and provided with a third circuit pattern,
wherein the first connection structure is electrically disconnected from the third circuit pattern, and
wherein the second connection structure is electrically connected to the third circuit pattern.

6. The semiconductor package of claim 1 ,
wherein the second circuit pattern comprises an integrated circuit that is of the same kind as an integrated circuit of the first circuit pattern.

7. A semiconductor package, comprising:
a substrate;
a first semiconductor chip mounted on the substrate and provided with a plurality of first connection vias arrayed in a first direction and a plurality of first dummy vias arrayed in the first direction;
a second semiconductor chip mounted on the first semiconductor chip and provided with a plurality of second connection vias arrayed in the first direction and a plurality of second dummy vias arrayed in the first direction;
a plurality of first connection terminals each interposed between the first semiconductor chip and the second semiconductor chip and coupled to one of the plurality of first connection vias and one of the plurality of second dummy vias; and
a plurality of second connection terminals each interposed between the first semiconductor chip and the second semiconductor chip and coupled to one of the plurality of first dummy vias and one of the plurality of second connection vias,
wherein:
the second semiconductor chip has a 2-fold rotational symmetry with respect to the first semiconductor chip such that in a first orientation, the plurality of first connection vias each vertically overlaps with one of the plurality of second connection vias and in a second orientation with the second semiconductor chip rotated relative to the first semiconductor chip, the plurality of first connection vias each vertically overlaps with one of the plurality of second dummy vias,
the first semiconductor chip has the same structure as the second semiconductor chip, and
the second semiconductor chip is laterally shifted from the first semiconductor chip in the first direction.

8. The semiconductor package of claim 7 ,
wherein, when viewed in plan view, the plurality of second connection vias each is overlapped with one of the plurality of first dummy vias, and
wherein the plurality of second dummy vias each is overlapped with one of the plurality of first connection vias.

9. The semiconductor package of claim 7 ,
wherein a number of the plurality of first connection vias is the same as a number of the plurality of first dummy vias.

10. The semiconductor package of claim 7 ,
wherein a number of the plurality of second connection vias is the same as a number of the plurality of second dummy vias.

11. The semiconductor package of claim 7 ,
wherein the first semiconductor chip comprises a first circuit pattern, and
wherein the first circuit pattern is electrically connected to the plurality of first connection vias and is electrically disconnected from the plurality of first dummy vias.

12. The semiconductor package of claim 7 ,
wherein the second semiconductor chip comprises a second circuit pattern, and
wherein the second circuit pattern is electrically connected to the plurality of second connection vias and is electrically disconnected from the plurality of second dummy vias.

13. A semiconductor package, comprising:
a substrate;
a first semiconductor chip mounted on the substrate and provided with a first circuit pattern;
a second semiconductor chip provided on the first semiconductor chip and provided with a second circuit pattern;
a first dummy via, a first connection via, a second dummy via and a second connection via in the listed sequence arranged in a first direction, the first connection via and the second connection via and the first dummy via and the second dummy via provided through the first semiconductor chip;
a third connection via, a third dummy via, a fourth connection via and a fourth dummy via in the listed sequence arranged in the first direction, the third connection via and the fourth connection via and the third dummy via and the fourth dummy via provided through the second semiconductor chip,
wherein:
the first connection via and the second connection via are electrically connected to the first circuit pattern and the first dummy via and the second dummy via are electrically disconnected from the first circuit pattern,
the third connection via and the fourth connection via are electrically connected to the

Assignees

• Lee In
• Samsung Electronics Co Ltd

Inventors

• Lee In

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title