Bump structures in semiconductor device and packaging assembly

Patent metadata

Field	Value
Publication number	US-9905524-B2
Application number	US-201113193969-A
Country	US
Kind code	B2
Filing date	Jul 29, 2011
Priority date	Jul 29, 2011
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A bump structure in a semiconductor device or a packing assembly includes an under-bump metallization (UBM) layer formed on a conductive pad of a semiconductor substrate. The UBM layer has a width greater than a width of the conductive pad.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate comprising a first conductive pad and a second conductive pad;
a first bump structure over and electrically coupled to the first conductive pad, wherein the first bump structure is wider than the first conductive pad; and
a second bump structure over and electrically coupled to the second conductive pad, a bump pitch existing from a center of the first bump structure to a center of the second bump structure,
wherein
the first conductive pad has a first width, the first bump structure has a first under-bump metallization (UBM) layer with a second width, the second width is greater than the first width, and
a cap layer over the first bump structure, wherein the cap layer exposes sidewalls of the first bump structure.

2. The semiconductor device of claim 1 , wherein a ratio between the second width and the bump pitch is between about 0.65 and about 0.8.

3. The semiconductor device of claim 1 , wherein a ratio between the first width and the bump pitch is between about 0.5 and 0.6.

4. The semiconductor device of claim 1 , further comprising a passivation layer between the first conductive pad and the first UBM layer, the passivation layer having a first opening exposing a portion of the first conductive pad.

5. The semiconductor device of claim 4 , wherein a ratio between the width of the first opening and the bump pitch is between about 0.3 and 0.4.

6. The semiconductor device of claim 4 , further comprising a protective layer between the passivation layer and the UBM layer, the protective layer covering the passivation layer and having a second opening exposing a portion of the first conductive pad.

7. The semiconductor device of claim 6 , wherein a ratio between the width of the second opening and the width of the first opening is between about 0.7 and 0.9.

8. The semiconductor device of claim 1 , wherein the first bump structure comprises a copper pillar on the first UBM layer.

9. The semiconductor device of claim 8 , wherein the cap layer comprises nickel, tin, tin-lead, gold, silver, palladium, indium, platinum, or an alloy.

10. The semiconductor device of claim 8 , wherein the first bump structure comprises a solder layer overlying the copper pillar.

11. A semiconductor device, comprising:
a semiconductor substrate comprising a conductive pad, the conductive pad having a first width;
a passivation layer over the conductive pad, wherein the passivation layer comprises an opening exposing a portion of the conductive pad;
a protective layer over the semiconductor substrate and exposing a portion of the conductive pad;
an under-bump metallization (UBM) layer over the protective layer and electrically coupled to the conductive pad, the UBM layer having a second width greater than the first width; and
a conductive pillar over the UBM layer,
wherein
the second width is at least 1.1 times the first width,
the conductive pillar is wider than the opening of the passivation layer, and
the UBM layer and the conductive pillar have substantially equal widths.

12. The semiconductor device of claim 11 , wherein the second width is greater than 1.2 times the first width.

13. The semiconductor device of claim 11 , wherein the second width is greater than 1.3 times the first width.

14. The semiconductor device of claim 11 , wherein the conductive pillar comprises a copper pillar.

15. The semiconductor device of claim 14 , further comprising a metal cap layer overlying the copper pillar.

16. A semiconductor device comprising:
an under-bump metallization (UBM) layer in contact with a conductive pad, wherein a width of the UBM layer is at least 1.1 times greater than a width of the conductive pad;
a protective layer over the conductive pad, wherein a portion of the protective layer is in contact with the conductive pad;
a conductive pillar over the UBM layer, wherein the conductive pillar is wider than the conductive pad, and a portion of a sidewall of the conductive pillar is coplanar with a portion of a sidewall of the UBM layer; and
a solder layer over the conductive pillar.

17. The semiconductor device of claim 16 , further comprising a passivation layer between the UBM layer and the conductive pad.

18. The semiconductor device of claim 17 , further comprising the protective layer between the passivation layer and the UBM layer.

19. The semiconductor device of claim 16 , wherein the conductive pillar comprises copper.

20. The semiconductor device of claim 16 , further comprising a cap layer between the solder layer and the conductive pillar.

Assignees

• Chuang Chita
• Chuang Yao Chun
• Lin Tsung Shu
• Kuo Chen Cheng
• Chen Chen Shien
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Chita
• Chuang Yao Chun
• Lin Tsung Shu
• Kuo Chen Cheng
• Chen Chen Shien

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/01953

  by etching · CPC title