Semiconductor device containing memory cells with a fuse in static random memory cell (SRAM) device and method of manufacturing same

Patent metadata

Field	Value
Publication number	US-9905512-B2
Application number	US-201615016360-A
Country	US
Kind code	B2
Filing date	Feb 5, 2016
Priority date	Mar 17, 2015
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

An object of the invention is to provide a semiconductor device having less cracking or peeling and a method of manufacturing the same. A fuse portion of a semiconductor device has bit lines electrically coupled to a SRAM memory cell. The bit lines are covered by an interlayer insulating film. As the interlayer insulating film, a boron-doped BPTEOS film is formed. The bit lines have thereabove a fuse. The fuse and the bit lines are electrically coupled to each other via contact plugs. The interlayer insulating film that covers the bit lines therewith is separated from the contact plugs.

First claim

What is claimed is:

1. A semiconductor device, comprising
a semiconductor substrate having a main surface;
wirings formed over the main surface of the semiconductor substrate and including a first wiring extending in one direction;
a fuse separated from the wirings in a direction separating from the main surface;
contact plugs including a first contact plug in contact with each of the first wiring and the fuse and electrically coupling the first wiring to the fuse;
a first interlayer insulating film containing boron formed on the first wiring; and
a second interlayer insulating film, distinct from the first interlayer insulating film, formed between the first interlayer insulating film and the first contact plug so as to separate the first interlayer insulating film from the first contact plug,
wherein the first interlayer insulating film and the second interlayer insulating film are formed between the fuse and the first wiring.

2. The semiconductor device according to claim 1 ,
wherein the wirings include a second wiring extending in the one direction,
wherein the first wiring and the second wiring are placed so that an end portion of the first wiring and an end portion of the second wiring are placed so as to face to each other with a distance in the one direction,
wherein the contact plugs include a second contact plug in contact with each of the second wiring and the fuse and electrically coupling the second wiring to the fuse,
wherein the first interlayer insulating film is formed so as to cover the second wiring while being separated from the second contact plug and is formed in a region located between the end portion of the first wiring and the end portion of the second wiring, and
wherein a portion of the first interlayer insulating film formed in a region located between the end portion of the first wiring and the end portion of the second wiring is separated from each of the first contact plug and the second contact plug.

3. The semiconductor device according to claim 1 ,
wherein the wirings include a second wiring extending in the one direction,
wherein the first wiring and the second wiring are placed so that an end portion of the first wiring and an end portion of the second wiring are placed so as to face to each other with a distance in the one direction,
wherein the contact plugs include a second contact plug in contact with each of the second wiring and the fuse and electrically coupling the second wiring to the fuse, and
wherein the first interlayer insulating film is formed so as to cover the second wiring while being separated from the second contact plug and is not formed in a region located between the end portion of the first wiring and the end portion of the second wiring.

4. The semiconductor device according to claim 1 ,
wherein the interlayer insulating films include a second-boron-containing second interlayer insulating film formed between the first interlayer insulating film and the fuse, and
wherein a concentration of the first boron contained in the first interlayer insulating film is set higher than a concentration of the second boron contained in the second interlayer insulating film.

5. The semiconductor device according to claim 1 ,
wherein the semiconductor substrate has, over the main surface thereof, a plurality of memory cells,
wherein the first interlayer insulating film covers the memory cells, and
wherein the wirings include, as the first wiring, a bit line electrically coupled to one of the memory cells.

6. The semiconductor device according to claim 5 ,
wherein the memory cells include a static random access memory cell.

7. The semiconductor device according to claim 1 ,
wherein a sidewall insulating film is formed so as to cover an end surface of the first interlayer insulating film.

8. A semiconductor device, comprising:
a semiconductor substrate having a main surface;
wirings formed over the main surface of the semiconductor substrate and including a first wiring extending in one direction;
a fuse separated from the wirings in a direction separating from the main surface;
contact plugs including a first contact plug in contact with each of the first wiring and the fuse and electrically coupling the first wiring to the fuse;
a first interlayer insulating film containing boron formed on the first wiring; and
a second interlayer insulating film, distinct from the first interlayer insulating film, formed between the fuse and the first interlayer insulating film;
wherein the first interlayer insulating film comprises a first portion and a second portion, wherein the first portion has first thickness in a first direction from the fuse to the first wiring and the second portion has a second thickness in the first direction, wherein the second thickness is smaller than the first thickness, and
wherein the first contact plug is in contact with the first wiring while penetrating through the second portion.

9. The semiconductor device according to claim 8 ,
wherein the semiconductor substrate has, over the main surface thereof, a plurality of memory cells,
wherein the first interlayer insulating film covers the memory cells; and
wherein the wirings include, as the first wiring, a bit line that is electrically coupled to one of the memory cells.

10. The semiconductor device according to claim 9 ,
wherein the memory cells include a static random access memory cell.

11. The semiconductor device according to claim 8 ,
wherein a sidewall insulating film covers an end surface of the first interlayer insulating film.

Assignees

• Renesas Electronics Corp

Inventors

• Iwasaki Toshifumi
• Maki Yukio

Classifications

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/071

  of dielectric parts thereof · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W20/493 Primary

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H01L21/76831

  Electricity · mapped topic