Package structure

Patent metadata

Field	Value
Publication number	US-9905508-B2
Application number	US-201715693198-A
Country	US
Kind code	B2
Filing date	Aug 31, 2017
Priority date	Dec 19, 2014
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A chip packaging structure includes a flexible circuit board, a first built-up structure, a second built-up structure, and a first solder resist layer. The flexible circuit board defines a bent area and a laminated area. The flexible circuit board includes a first dielectric layer. The first dielectric layer includes a first conductive pattern, a bearing layer opposite to the first conductive pattern and corresponding to the laminated area. The first built-up structure is located on the first conductive pattern and corresponds to the laminated area, and includes a second dielectric layer and a second conductive pattern electrically connected with the first conductive pattern. The second built-up structure is located on the bearing layer and corresponds to the laminated area, and includes a third dielectric layer and a third conductive pattern electrically connected with the first conductive pattern. The first solder resist layer covers the second conductive pattern.

First claim

What is claimed is:

1. A package structure comprising:
a flexible circuit board defining a bent area and a laminated area and comprising:
a first dielectric layer;
a first conductive pattern located at a side of the first dielectric layer, comprising a connection terminal located at an end of the bent area away from the laminated area;
a bearing layer located at a side of the first dielectric layer opposite to the first conductive pattern, corresponding to the laminated area; and
a first built-up structure located on the first conductive pattern and corresponding to the laminated area, the first built-up structure comprising a second dielectric layer and a second conductive pattern electrically connected with the first conductive pattern via first conductive holes in the second dielectric layer;
a second built-up structure located on the bearing layer and corresponding to the laminated area, the second built-up structure comprising a third dielectric layer and a third conductive pattern electrically connected with the first conductive pattern via second conductive holes in the third dielectric layer; wherein the second dielectric layer, the third dielectric layer, the second conductive pattern, and the third conductive pattern correspond only to the laminated area; and
a first solder resist layer covering the second conductive pattern and defining a plurality of openings, a portion of the second conductive pattern exposed from the openings defining a plurality of first pads.

2. The package structure of claim 1 , further comprising a second solder resist layer, wherein the second solder resist layer covers third conductive pattern, the second solder resist layer defines a plurality of openings, a portion of the third conductive pattern exposed from the openings defines a plurality of second pads.

3. The package structure of claim 1 , further comprising a first cover layer and a second cover layer, wherein the first cover layer covers the first conductive pattern, the first cover layer defines a plurality of openings, the connection terminal is exposed from the openings, the second cover layer cover the bearing layer, the first dielectric layer exposed from the bearing layer, and the first dielectric layer corresponding to the bent area.

4. The package structure of claim 3 , wherein the third dielectric layer is located between the second cover layer and the third conductive pattern.

5. The package structure of claim 3 , wherein the bearing layer defines a plurality of first openings, the second conductive holes correspond to the first openings, and the second conductive holes and the bearing layer are separated from each other.

6. The package structure of claim 5 , further comprising a plurality of first and second blind holes, wherein the first blind holes run through the second conductive pattern, the second dielectric layer, and the first cover layer, a portion of the first conductive pattern is exposed from the first blind holes, the second blind holes run through the third conductive pattern, the third dielectric layer, the second cover layer, the first openings, and the first dielectric layer, a portion of the first conductive pattern is exposed from the second blind holes.

7. The package structure of claim 6 , the second blind holes correspond to the first openings respectively.

8. The package structure of claim 1 , wherein a thickness of the bearing layer is greater than a thickness of the first conductive pattern.

9. The package structure of claim 1 , wherein the first dielectric layer is made of flexible insulating materials.

10. The package structure of claim 1 , further comprising a chip on the first solder resist layer, wherein the chip comprises a plurality of electrode pads, and each of the electrode pads corresponds to and electrically connects to one of the first pads.

Assignees

• Qi Ding Tech Qinhuangdao Co Ltd
• Zhen Ding Tech Co Ltd

Inventors

• Su wei shuo

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title