Semiconductor devices and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9905468-B2
Application number	US-201615061200-A
Country	US
Kind code	B2
Filing date	Mar 4, 2016
Priority date	May 13, 2015
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
forming a fin by forming a first trench of a first depth by etching a substrate;
forming a first device isolating layer in the first trench;
forming a second trench of a second depth that is greater than the first depth by etching the first device isolating layer and the substrate;
forming a second device isolating layer in the second trench;
forming a plurality of dummy gates on the fin;
forming a mask that extends on the plurality of dummy gates and comprises an opening exposing one of the plurality of dummy gates;
forming a third trench of a third depth that is less than the first depth by etching the one of the plurality of dummy gates exposed by the mask using the mask as an etch mask, and by etching a portion the fin that is below the one of the plurality of dummy gates exposed by the mask; and
forming a third device isolating layer in the third trench.

2. The method of claim 1 , wherein the first device isolating layer, the second device isolating layer and the third device isolating layer comprise materials different from one another.

3. The method of claim 2 , wherein the first device isolating layer comprises a Tonen SilaZene (TOSZ) or flowable chemical vapor deposition (FCVD) oxide, and the second device isolating layer comprises a high density plasma (HDP) oxide or an undoped silicate glass (USG) oxide.

4. The method of claim 3 , wherein the third device isolating layer comprises nitride.

5. The method of claim 3 , wherein the third device isolating layer comprises a TOSZ or FCVD oxide and has a lower etching resistance than that of the first device isolating layer.

6. The method of claim 1 , further comprising:
performing a first annealing process at a first temperature after forming the first device isolating layer and before forming the second device isolating layer; and
performing a second annealing process at a second temperature that is lower than the first temperature after forming the third device isolating layer.

7. The method of claim 1 , wherein an upper portion of the second device isolating layer is in direct contact with the first device isolating layer.

8. The method of claim 1 , further comprising forming a fourth device isolating layer on the third device isolating layer, wherein the fourth device isolating layer comprises a first region and a second region, and a width of the first region is different from that of the second region.

9. The method of claim 8 , wherein the second region is between the third device isolating layer and the first region, and the width of the first region is greater than that of the second region.

10. The method of claim 6 , wherein the first temperature is 1000° C. or above, and the second temperature is 700° C. or below.

11. A method of forming a semiconductor device comprising:
forming a fin protruding from a substrate;
forming a first device isolating layer on a side of the fin and on the substrate; and
forming a second device isolating layer extending through the first device isolating layer and separating a first active region comprising the fin from a second active region, the second device isolating layer comprising a lower portion that extends from a lower surface of the first device isolating layer into the substrate, and the second device isolating layer comprising a material different from the first device isolating layer,
wherein upper surfaces of the fin, the first device isolating layer and the second device isolating layer are coplanar after forming the second device isolating layer.

12. The method of claim 11 , further comprising:
forming a first gate, a second gate and a third gate that traverse the fin, after forming the second device isolating layer, the second gate being, between the first gate and the third gate;
forming first spacers, second spacers and third spacers on, respective sides of the first gate, the second gate and the third gate;
removing the second gate to form an opening between the second spacers; and
forming a third device isolating layer in the opening, the third device isolating layer comprising a lower portion that extends into the fin and a lowermost surface that is higher than a lowermost surface of the first device isolating layer.

13. The method of claim 12 , wherein the third device isolating layer comprises a material different from the first device isolating layer and the second device isolating layer.

14. The method of claim 13 , wherein the first device isolating layer comprises a Tonen SilaZene (TOSZ) or flowable chemical vapor deposition (FCVD) oxide,
wherein the second device isolating layer comprises a high density plasma (HDP) oxide or an doped silicate glass (USG) oxide, and
wherein the third device isolating layer comprises nitride, TOSZ or FCVD oxide.

15. The method of claim 11 , wherein a side of the second device isolating layer contacts the first device isolating layer.

16. The method of claim 11 , wherein the first device isolating layer comprises a Tonen SilaZene (TOSZ) or flowable chemical vapor deposition (FCVD) oxide, and
wherein the second device isolating layer comprises a high density plasma (HDP) oxide or an undoped silicate glass (USG) oxide.

17. The method of claim 11 , further comprising recessing the first device isolating layer and the second device isolating layer after firming the second device isolating layer to expose the side of the fin.

18. A method of forming a semiconductor device comprising:
forming a fin protruding from a substrate;
forming a first device isolating layer on a side of the fin, the first device isolating layer comprising a lowermost surface at a first depth from an upper surface of the fin and comprising a first material;
forming a second device isolating layer extending through, the first device isolating layer, the second device isolating layer comprising a lowermost, surface at a second depth from the upper surface of the fin that is greater than the first depth and comprising a second material and the upper surface of the fin being coplanar with upper surfaces of the first device isolating layer and the second device isolating layer after forming the second device isolating layer;
forming a first gate and a second gate traversing the fin; and
forming a third device isolating layer between the first gate and the second gate, the third device isolating layer extending into the fin, comprising a lowermost surface at a third depth from the upper surface of the fin that is less than the first depth and comprising a third material that is different from the first material and the second material.

19. The method of claim 18 , wherein the first material comprises a Tonen SilaZene (TOSZ) or flowable chemical vapor deposition (FCVD) oxide, and
wherein the second material comprises a high density plasma (HDP) oxide or an undoped silicate glass (USG) oxide.

20. The method of claim 19 , wherein the third material comprises nitride.

Assignees

• Kim Sung Min
• Paak Sunhom Steve
• Shin Heon Jong
• Cha Dong Ho
• Samsung Electronics Co Ltd

Inventors

• Kim Sung Min
• Paak Sunhom Steve
• Shin Heon Jong
• Cha Dong Ho

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L21/823481

  Electricity · mapped topic

• H01L21/823431 Primary

  Electricity · mapped topic

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title