Memory system and program operation method based on program speed information

Patent metadata

Field	Value
Publication number	US-9905304-B2
Application number	US-201615000481-A
Country	US
Kind code	B2
Filing date	Jan 19, 2016
Priority date	Sep 3, 2015
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

There are provided a memory system having improved reliability and an operating method thereof. A memory system includes a semiconductor memory device including a memory cell array having a plurality of pages, and a controller for sequentially transmitting, to the semiconductor memory device, physical block addresses of pages to be programmed among the plurality of pages. In the memory system, the semiconductor memory device selects a page corresponding to each of the physical block addresses among the plurality of pages according to previously stored program speed information, and performs a program operation on the selected page.

First claim

What is claimed is:

1. A memory system comprising:
a semiconductor memory device configured to include a memory cell array having a plurality of pages; and
a controller configured to sequentially transmit, to the semiconductor memory device, physical block address of page to be programmed among the plurality of pages,
wherein the semiconductor memory device selects a word line corresponding to the physical block addresses among the plurality of pages according to previously stored program speed information, and performs a program operation on the selected word line,
wherein each of the plurality of pages includes slow cells and fast cells,
wherein the program speed information is a list of the plurality of pages in a descending order of a ratio of the slow cells included in each page, and
wherein the selected word line has a highest rate of the slow cells.

2. The memory system of claim 1 , wherein the program speed information is stored in a CAM area among the plurality of pages.

3. The memory system of claim 2 , wherein the semiconductor memory device further includes a program speed information storage unit configured to store the program speed information.

4. The memory system of claim 3 , wherein, if power is supplied to the memory system, the semiconductor memory device loads the program speed information stored in the CAM area into the program speed information storage unit.

5. The memory system of claim 1 , wherein the program speed information includes information in which the physical block addresses are mapped to the plurality of pages according to program speeds.

6. The memory system of claim 1 , wherein the semiconductor memory device further includes an address decoder configured to select any one page among the plurality of pages by decoding the physical block address.

7. The memory system of claim 6 , wherein if power is supplied to the memory system, the semiconductor memory device sets the address decoder by using the program speed information.

8. The memory system of claim 1 , wherein the controller further includes a host interface unit configured to communicate with a host connected to the memory system.

9. The memory system of claim 8 , wherein the controller further includes a read only memory (ROM) configured to store code data for interfacing with the host.

10. A method of operating a semiconductor memory device including a memory cell array having a plurality of pages, wherein each of the plurality of pages includes slow cells and fast cells, the method comprising:
loading program speed information stored in a CAM area of the memory cell array if power is supplied to the memory system,
wherein the program speed information is a list of the plurality of pages in a descending order of a ratio of the slow cells included in each page;
determining a page having a highest ratio of the slow cells among the plurality of pages according to the program speed information; and
performing a program operation on the determined page.

11. The method of claim 10 , wherein the program speed information includes information in which the physical block addresses are sequentially mapped to the plurality of pages from a page having the slowest program speed.

12. The method of claim 10 , wherein in the loading of the program speed information stored in the CAM area of the memory cell array, an address decoder for selecting any one page among the plurality of pages by decoding the physical block address is set according to the program speed information.

13. The method of claim 10 , wherein the loading of the program speed information stored in the CAM area of the memory cell array is performed in an auto CAM read operation during a reset operation of the memory system.

14. The method of claim 10 , wherein the determining the page having a slowest program speed comprises:
determining a program order of the plurality of pages, based on the program speed information; and
selecting the page having a slowest program speed among the plurality of pages according to the program order.

15. The method of claim 14 , wherein the program speed information includes program speeds of a plurality of memory cells associated with a page included in the memory cell array.

16. The method of claim 14 , wherein the program speed information includes a listing of word lines associated with a slowest page to a fastest page.

17. The method of claim 14 , wherein a control logic selects which pages are to be programmed based on the program speed information, wherein the program speed information is loaded from a program speed information storage unit.

18. The method of claim 14 , wherein the program order of the plurality of pages is from slowest to fastest page.

19. The method of claim 18 , wherein a semiconductor memory device selects a page to perform a program operation on according to previously stored program speed information, where a slowest page is selected and each page selected after a first page has a faster programming speed.

20. The method of claim 14 , wherein program speed information is stored in a CAM area of the memory cell array.

Assignees

• Sk Hynix Inc

Inventors

• Park Eun Young

Classifications

• G11C15/00

  Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores · CPC title

• G11C2211/5646

  Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page" · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/32 Primary

  Timing circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title