Nonvolatile memory device and operating method of nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-9905299-B2
Application number	US-201615370079-A
Country	US
Kind code	B2
Filing date	Dec 6, 2016
Priority date	Dec 7, 2015
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a row decoder circuit connected to the memory cell array through a plurality of word lines; and a page buffer circuit connected to the memory cell array through bit lines. The row decoder circuit applies read voltages to a selected word line during a read operation. During a read operation performed with respect to each of N logical pages (N being a positive integer) of memory cells connected to the selected word line, the row decoder circuit applies a read voltage from among adjacent N read voltages to the selected word line without applying read voltages other than the adjacent N read voltages to the selected word line. The adjacent N read voltages include a second highest read voltage among the read voltages.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a memory cell array comprising a plurality of memory cells;
a row decoder circuit connected to the memory cell array through a plurality of word lines and configured to apply read voltages to a selected word line during a read operation; and
a page buffer circuit connected to the memory cell array through bit lines,
wherein during a read operation performed with respect to each of N logical pages (N being a positive integer) of memory cells connected to the selected word line, the row decoder circuit is configured to apply a read voltage from among adjacent N read voltages to the selected word line without applying the other N-1 read voltages other than the read voltage to the selected word line, and
wherein the adjacent N read voltages comprise a second highest read voltage among the read voltages.

2. The nonvolatile memory device of claim 1 , wherein the adjacent N read voltages comprise a highest read voltage among the read voltages.

3. The nonvolatile memory device of claim 1 , wherein the adjacent N read voltages do not comprise a highest read voltage among the read voltages.

4. The nonvolatile memory device of claim 1 , wherein during read operations performed with respect to different logical pages among the N logical pages, the row decoder circuit is configured to apply different read voltages from among the adjacent N read voltages to the selected word line.

5. The nonvolatile memory device of claim 1 , wherein during read operations performed with respect to the N logical pages, the row decoder circuit is configured to apply to the selected word line read voltages of a number less than or equal to an upper limit or a lower limit corresponding to a value of 2 N /N.

6. The nonvolatile memory device of claim 1 , wherein the adjacent N read voltages are determined according to information received from an external device.

7. The nonvolatile memory device of claim 1 , wherein the memory cell array comprises a three-dimensional structure, and wherein each of the plurality of memory cells comprises a charge trap layer.

8. The nonvolatile memory device of claim 7 , wherein the plurality of memory cells are stacked in a direction perpendicular to a substrate.

Assignees

• Seol Changkyu
• Kong Junjin
• Ra Youngsuk
• So Hyejeong
• Son Hong Rak
• Samsung Electronics Co Ltd

Inventors

• Seol Changkyu
• Kong Junjin
• Ra Youngsuk
• So Hyejeong
• Son Hong Rak

Classifications

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C2029/1204

  Bit line control · CPC title