Host for controlling frequency of operating clock signal of display driver IC and system including the same

Patent metadata

Field	Value
Publication number	US-9905193-B2
Application number	US-201414329207-A
Country	US
Kind code	B2
Filing date	Jul 11, 2014
Priority date	Jul 11, 2013
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A display driver integrated circuit (DDI) for driving a display of image data on a display panel, an application processor (AP), a system including the DDI and the AP, and methods of operating the same are provided. The application processor includes: a controller configured to obtain a frequency of a data transmission timing control received from a display driver integrated circuit (DDI), and to generate, based on the obtained frequency, a frequency control signal for adjusting a frequency related to an operating clock signal for the DDI; a transmitter configured to transmit the generated frequency control signal to the DDI; and a frequency calculation circuit including: a detector configured to receive the data transmission timing control signal from the DDI, and a frequency calculator configured to calculate a frequency of the received data transmission timing control signal.

First claim

What is claimed is:

1. An application processor for a display system of a portable device that displays image data on a display panel, the application processor comprising:
a controller configured to obtain a frequency of a signal received from a display driver integrated circuit (DDI), and to generate, based on the obtained frequency, a frequency control signal for adjusting a frequency of an internal clock signal output by an operating clock of the DDI, to adjust the frequency of the signal received from the DDI; and
a transmitter configured to transmit the generated frequency control signal to the DDI.

2. The application processor as claimed in claim 1 , wherein:
the received signal is a tearing effect signal; and
the controller is configured to control the transmitter to transmit the image data to the DDI in response to the received tearing effect signal.

3. The application processor as claimed in claim 1 , wherein the controller is configured to generate the frequency control signal in response to the obtained frequency being outside of a predetermined operating frequency range for the DDI.

4. The application processor as claimed in claim 1 , further comprising:
a frequency calculation circuit configured to receive the signal from the DDI, and to calculate, based on a reference clock signal, the frequency of the received signal,
wherein the controller is configured to generate the frequency control signal based on the calculated frequency.

5. The application processor as claimed in claim 4 , wherein the frequency calculation circuit comprises:
a frequency counter configured to determine a count value, based on the reference clock signal, of a period of the received signal; and
a frequency calculator configured to calculate, based on the determined count value, the frequency of the received signal.

6. The application processor as claimed in claim 1 , wherein the controller is a central processing unit (CPU).

7. The application processor as claimed in claim 1 , wherein the controller is an image processing circuit.

8. An application processor for a display system of a portable device that displays image data on a display panel, the application processor comprising:
a controller configured to obtain a frequency of a data transmission timing control signal received from a display driver integrated circuit (DDI), and to generate, based on the obtained frequency, a frequency control signal for adjusting a frequency of an internal clock signal output by an operating clock of the DPI, to adjust the frequency of the data transmission timing control signal;
a transmitter configured to transmit the generated frequency control signal to the DDI; and
a frequency calculation circuit comprising:
a detector configured to receive the data transmission timing control signal from
the DDI, and a frequency calculator configured to calculate the frequency of the received data transmission timing control signal.

9. The application processor as claimed in claim 8 , wherein the frequency calculator is configured to output the calculated frequency to the controller.

10. The application processor as claimed in claim 8 , wherein the frequency calculation circuit further comprises:
a frequency comparer configured to determine whether the calculated frequency is within a predetermined operating frequency range for the DDI, to generate a control signal according to the determining, and to output, to the controller, the generated control signal.

11. The application processor as claimed in claim 10 , wherein:
the frequency comparer generates, as the control signal, a first control signal in response to the calculated frequency being lower than the predetermined operating frequency range, a second control signal in response to the calculated frequency being within the predetermined operating frequency range, and a third control signal in response to the calculated frequency being higher than the predetermined operating frequency range.

12. The application processor as claimed in claim 8 , wherein the frequency calculation circuit further comprises:
a frequency counter configured to determine a count value, based on a reference clock signal, of a period of the received data transmission timing control signal,
wherein the frequency calculator is configured to calculate, based on the determined count value, the frequency of the received data transmission timing control signal.

13. The application processor as claimed in claim 12 , wherein the detector comprises an edge detector configured to detect the period of the received data transmission timing control signal based on a rising edge or a falling edge of the received data transmission timing control signal.

14. The application processor as claimed in claim 12 , wherein the frequency calculation circuit further comprises:
a frequency divider configured to divide the reference clock signal by a predetermined factor,
wherein the frequency counter is configured to determine the count value based on the divided reference clock signal.

15. A display system that displays image data, the display system comprising:
an application processor comprising:
a first controller configured to obtain, from a frequency calculation circuit, a frequency of a signal provided by a display driver integrated circuit (DDI), and to generate, based on the obtained frequency, a first frequency control signal for adjusting a frequency of an internal clock signal output by an operating clock of the DDI, to adjust the frequency of the signal provided by the DDI, and
a transmitter configured to transmit the generated first frequency control signal to the DDI;
the frequency calculation circuit configured to receive the signal from the DDI, to calculate, based on a reference clock signal, the frequency of the received signal, and to provide the calculated frequency to the first controller; and
the DDI configured to drive a display of the image data on a display panel, the DDI comprising:
a control signal generator configured to generate the signal based on the internal clock signal, and to provide the generated signal to the application processor and the frequency calculation circuit;
a receiver configured to receive, in response to the provided signal, the first frequency control signal from the application processor; and a second controller configured to output, based on the received first frequency control signal, a second frequency control signal to adjust the frequency of the internal clock signal.

16. The display system as claimed in claim 15 , wherein the display system is a portable device and the application processor is a host.

17. The display system as claimed in claim 15 , wherein the signal is a tearing effect signal.

18. The display system as claimed in claim 15 , wherein the DDI further comprises an oscillator configured to output the internal clock signal,
wherein the DDI is configured to adjust a frequency of the internal clock signal according to the second frequency control signal.

19. The display system as claimed in claim 15 , wherein the DDI is configured to adjust, according to the second frequency control signal and the internal clock signal, a frequency of the generated signal.

20. The display system as claimed in claim 19 , wherein the DDI is configured to adjust the frequency of the generated signal according to a ratio between a deviated frequency of the internal clock signal and the frequency of the generated signal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Oh Hee Tae
• Kim Dong Hwy
• Kim Do Kyung

Classifications

• G06F3/14

  Digital output to display device {; Cooperation and interconnection of the display device with other functional units} · CPC title

• G09G2360/18

  Use of a frame buffer in a display terminal, inclusive of the display panel · CPC title

• G09G5/006 Primary

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title