Shift register, driving method, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-9905179-B2
Application number	US-201514786046-A
Country	US
Kind code	B2
Filing date	Mar 20, 2015
Priority date	Oct 20, 2014
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A shift register, a driving method, a gate driving circuit and a display device. The shift register comprises an input terminal (STV_IN), a reset terminal (STV_RES), a trigger terminal (CLK_IN), an output terminal (STV_OUT), an input module connected to the input terminal (STV_IN) and the reset terminal (STV_RES) and configured to deliver a signal received from the input terminal (STV_IN) or a signal received from the reset terminal (STV_RES) to an output module under the control of an external signal (U 2 D, D 2 U); a trigger module connected to the input terminal (STV_IN), the reset terminal (STV_RES) and the trigger terminal (CLK_IN) and configured to deliver a signal received from the trigger terminal (CLK_IN) to the output module when a signal is received from the input terminal (STV_IN) or from the reset terminal (STV_RES); and the output module connected to the input module, the trigger module and the output terminal (STV_OUT) and configured to flip a signal outputted from the output terminal (STV_OUT) between an output state and a reset state according to a signal from the input module under the trigger of the signal from the trigger module. The trigger signal is filtered out when no signal is inputted by setting the trigger module or the trigger unit, such that remaining circuits keep in a steady state holding state, which is benefit for reducing of power consumption.

First claim

What is claimed is:

1. A shift register comprising an input terminal, a reset terminal, a trigger terminal and an output terminal, further comprising:
an input module connected to the input terminal and the reset terminal and with an output terminal connected to a first input terminal of an flip-flop output module, and configured to deliver a signal received from the input terminal or a signal received from the reset terminal to the first input terminal of the flip-flop output module under the control of an external signal;
a trigger module connected to the input terminal, the reset terminal and the trigger terminal with an output terminal connected to a second input terminal of the flip-flop output module, and configured to deliver a signal received from the trigger terminal to the second input terminal of the flip-flop output module when a signal is received from the input terminal or from the reset terminal; and
the flip-flop output module connected to the input module, the trigger module and the output terminal and configured to flip a signal outputted from the output terminal between an output state and a reset state according to the signal from the input module under the trigger of the signal from the trigger module.

2. The shift register of claim 1 , wherein the trigger module comprises a first NOR gate and a second NOR gate,
a first input terminal of the first NOR gate is connected to the input terminal of the shift register,
a second input terminal of the first NOR gate is connected to the reset terminal of the shift register,
an output terminal of the first NOR gate is connected to a first input terminal of the second NOR gate,
a second input terminal of the second NOR gate is connected to the trigger terminal of the shift register, and
an output terminal of the second NOR gate is used as the output terminal of the trigger module and is connected to the second input terminal of the flip-flop output module.

3. The shift register of claim 2 , wherein the flip-flop output module comprises a first tri-state NOT gate, a second tri-state NOT gate, a first inverter and a second inverter;
an input terminal of the first inverter, a non-inverting control terminal of the first tri-state NOT gate and an inverting control terminal of the second tri-state NOT gate are connected to the output terminal of the trigger module;
an output terminal of the first inverter is connected to an inverting control terminal of the first tri-state NOT gate and a non-inverting control terminal of the second tri-state NOT gate;
an output terminal of the first tri-state NOT gate and an output terminal of the second tri-state NOT gate are connected to an input terminal of the second inverter;
an output terminal of the second inverter is connected to an input terminal of the second tri-state NOT gate and the output terminal of the shift register;
an input terminal of the first tri-state NOT gate is connected to the output terminal of the input module.

4. The shift register of claim 3 , wherein the input module comprises a first switching element, a second switching element, a third switching element and a fourth switching element;
the input terminal of the shift register is connected to a first terminal of the third switching element and a second terminal of the first switching element;
the reset terminal of the shift register is connected to a second terminal of the fourth switching element and a first terminal of the second switching element;
the first input terminal of the flip-flop output module is connected to a second terminal of the third switching element, a first terminal of the first switching element, a first terminal of the fourth switching element and a second terminal of the second switching element;
a control terminal of the first switching element and a control terminal of the fourth switching element are connected to a first external signal, and
a control terminal of the second switching element and a control terminal of the third switching element are connected to a second external signal.

5. The shift register of claim 4 , wherein the first switching element and the second switching element are N channel thin film transistors, the third switching element and the fourth switching element are P channel thin film transistors.

6. A driving method for a shift register of claim 4 , comprising the trigger module delivering a signal received from the trigger terminal to the flip-flop output module when a signal is received at the input terminal, such that the flip-flop output module flips the signal outputted from the output terminal to the output state according to the signal from the input terminal under the trigger of the signal delivered by the trigger module;
the trigger module delivering a signal received from the trigger terminal to the flip-flop output module when a signal is received at the reset terminal, such that the flip-flop output module flips the signal outputted from the output terminal to the reset state according to the signal from the input terminal under the trigger of the signal delivered by the trigger module,
wherein the first external signal is at a high level and the second external signal is at a low level,
the output terminal of the input module is at a low level when the input terminal is at a low level, and is at a high level when the input terminal is at a high level;
the output terminal of the trigger module is at a low level when the input terminal and the reset terminal are both at a low level, is at a high level when one of the input terminal and the reset terminal is at a high level and the trigger terminal is at a low level, and is at a low level when one of the input terminal and the reset terminal is at a high level and the trigger terminal is at a high level;
the flip-flop output module forms a latch and the flip-flop output terminal of the output module is at a level same as that at the output terminal of the input module when the output terminal of the trigger module is at a high level; and the flip-flop output module forms a steady state holding circuit and the output terminal of the flip-flop output module is at a level independent of that at the output terminal of the input module when the output terminal of the trigger module is at a low level.

7. A driving method for a shift register of claim 4 , comprising the trigger module delivering a signal received from the trigger terminal to the flip-flop output module when a signal is received at the input terminal, such that the flip-flop output module flips the signal outputted from the output terminal to the output state according to the signal from the input terminal under the trigger of the signal delivered by the trigger module;
the trigger module delivering a signal received from the trigger terminal to the flip-flop output module when a signal is received at the reset terminal, such that the flip-flop output module flips the signal outputted from the output terminal to the reset state according to the signal from the input terminal under the trigger of the signal delivered by the trigger module,
wherein the first external signal is at a low level and the second external signal is at a high level,
the output terminal of the input module is at a low level when the input terminal is at a low level, and is at a high level when the input terminal is at a high level;
the output terminal of the trigger module is at a low level when the input terminal and the reset terminal are both at a low level, is at a high level when one of the input terminal and the reset terminal is at a high level and the trigger terminal is at a low level, and is at a low level when one of the input terminal and the reset terminal is at a high level and the trigger terminal is at a high level;
the flip-

Assignees

• Boe Technology Group Co Ltd
• Chengdu Boe Optoelect Tech Co

Inventors

• Hu Like
• Qi Xiaojing

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title