System on chip

US9904802B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9904802-B2
Application numberUS-201214647089-A
CountryUS
Kind codeB2
Filing dateNov 23, 2012
Priority dateNov 23, 2012
Publication dateFeb 27, 2018
Grant dateFeb 27, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system on chip having two or more responder units and two or more protection units is provided. Each of the responder units comprises a set of responder elements. Each of the protection units is associated with and protects one of the responder units and is arranged to provide a group mapping. The group mapping assigns one or more group identifiers to each of the responder elements of the respective responder unit.

First claim

Opening claim text (preview).

The invention claimed is: 1. A system on chip, comprising: two or more responder units; and two or more protection units, wherein each of said responder units comprises a set of responder elements including first, second, third, and fourth responder elements, each of said protection units is associated with and protects one of said responder units and is arranged to: provide a group mapping, wherein said group mapping assigns one or more group identifiers to each responder element of a respective responder unit and at least two of said responder elements of the set of responder elements of each of the responder units are assigned the same group identifier by a group identifier list, wherein the first and second responder elements provide a first function and are assigned a first group identifier, and the third and fourth responder elements provide a second function and are assigned a second group identifier, wherein the first and second functions are different, provide a group authorization list, wherein said group authorization list assigns a set of access requirements to each of said group identifiers, wherein the set of access requirements includes allowing a first requestor access to a first target responder element of the target responder elements only during specific time slices and inhibiting access during other time slices, receive a request for access to one or more target responder elements among the responder elements of the respective responder unit, for each of said target responder elements, determine a corresponding one or more group identifiers from said group mapping and further determine a corresponding one or more sets of access requirements from said group authorization list, and compare said request with respect to the determined set of access requirements, to generate a request evaluation result. 2. The system on chip of claim 1 , wherein said group mapping or said group authorization list or both are static. 3. The system on chip of claim 2 , wherein one or more of the group mapping and the group authorization list are configured in non-modifiable hardware. 4. The system on chip of claim 2 , further comprising a set of registers lockable against further modifications after being programmed, for configuring said group mapping and group authorization list by programming said set of registers, and subsequent locking of said set of registers. 5. The system on chip of claim 1 , wherein said two or more protection units include a first protection unit and a second protection unit, and the group mapping provided by the first protection unit differs from the group mapping provided by the second protection unit. 6. The system on chip of claim 1 , wherein said two or more protection units include a first protection unit and a second protection unit, and the group authorization list provided by the first protection unit differs from the group authorization list provided by the second protection unit. 7. The system on chip of claim 1 , wherein the group authorization list used by at least one of the protection units is stored in a respective protection unit. 8. The system on chip of claim 7 , further comprising: a request analysis unit arranged to: determine relevant protection data on the basis of said request and on the basis of a system authorization list comprising multiple entries, and provide selector criteria to a selected protection unit, wherein said selector criteria is based on the determined relevant protection data and enables the selected protection unit to determine said corresponding one or more group identifiers from said group mapping and further determine said corresponding one or more sets of access requirements from said group authorization list stored in the selected protection unit. 9. The system on chip of claim 1 , wherein the group authorization list used by at least one of the protection units is provided by another unit within the system on chip. 10. The system on chip of claim 2 , wherein said group mapping is implemented by combinatorial logic or masks enabling responder elements located at non-contiguous addresses or varying address offsets to be mapped to the same group identifier. 11. The system on chip of claim 1 , wherein each of said responder elements of the set of responder elements has an address and is addressable individually by means of the responder element address. 12. The system on chip of claim 1 , wherein said request evaluation result is indicative of an extent to which said request conforms to said determined one or more sets of access requirements. 13. The system on chip of claim 1 , wherein each of said protection units is further arranged to perform one or more of the following in dependence on said evaluation result: grant said request to an associated responder unit or corresponding target responder elements; refuse said request to the associated responder unit or the corresponding target responder elements; abort the access requested by said request to the associated responder unit or the corresponding target responder elements; generate an error indication. 14. The system on chip of claim 13 , wherein each of said protection units is arranged to provide further information about a refused or aborted request to another unit for error processing or recording within the system on chip. 15. A system on chip, comprising: two or more responder units; and two or more protection units, wherein each of said responder units comprises a set of responder elements, each of said protection units is associated with and protects one of said responder units and is arranged to: provide a group mapping, wherein said group mapping assigns one or more group identifiers to each responder element of a respective responder unit and at least two of said responder elements of the set of responder elements of each of the responder units are assigned the same group identifier by a group identifier list, wherein a first responder element and a second responder element provide a first function and are assigned a first group identifier, and a third responder element and a fourth responder element provide a second function and are assigned a second group identifier, wherein the first and second functions are different, provide a group authorization list, wherein said group authorization list assigns a set of access requirements to each of said group identifiers wherein the group authorization list used by at least one of the protection units is provided by another unit within the system on chip, receive a request for access to one or more target responder elements among the responder elements of the respective responder unit, for each of said target responder elements, determine a corresponding one or more group identifiers from said group mapping and further determine a corresponding one or more sets of access requirements from said group authorization list, and compare said request with respect to the determined set of access requirements, to generate a request evaluation result, wherein the group authorization list is provided by a request analysis unit arranged to receive from a requesting actor said request, wherein said request analysis unit is further arranged to determine relevant protection data on the basis of said request and on the basis of a system authorization list comprising multiple entries, wherein said determining of said relevant protection data comprises, for each entry of said system authorization list, to identify entries related to the actor, and to identify entries related to a target responder unit, and wherein said request an

Assignees

Inventors

Classifications

  • to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title

  • Intellectual property [IP] blocks or IP cores · CPC title

  • G06F21/74Primary

    operating in dual or compartmented mode, i.e. at least one secure mode · CPC title

  • to a system of files or objects, e.g. local or distributed file system or database · CPC title

  • G06F21/71Primary

    to assure secure computing or processing of information · CPC title

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What does patent US9904802B2 cover?
A system on chip having two or more responder units and two or more protection units is provided. Each of the responder units comprises a set of responder elements. Each of the protection units is associated with and protects one of the responder units and is arranged to provide a group mapping. The group mapping assigns one or more group identifiers to each of the responder elements of the res…
Who is the assignee on this patent?
Rohleder Michael, Singer Stefan, Thanner Manfred, and 1 more
What technology area does this patent fall under?
Primary CPC classification G06F21/74. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 27 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).