Memory system, host system, and method of performing write operation in memory system

Patent metadata

Field	Value
Publication number	US-9904628-B2
Application number	US-201414533655-A
Country	US
Kind code	B2
Filing date	Nov 5, 2014
Priority date	Nov 27, 2013
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A write operation is performed in a memory system by encoding, in the memory system, original data transmitted from a host system, according to a first type of host command, to produce an encoding result, transmitting information about the encoding result to the host system after the encoding, and writing the encoding result or the original data into a nonvolatile memory device, according to a second host command, wherein the second host command is transmitted from the host system based on the information about the encoding result.

First claim

What is claimed is:

1. A method of operating a memory system including a random access memory (RAM) and a non-volatile memory device, the method comprising:
receiving a first host command and original data from a host system;
storing the original data in the RAM in response to the first host command;
encoding the original data stored in the RAM to generate an encoding result;
transmitting information about the encoding result to the host system after the encoding of the original data;
receiving a second command from the host system, wherein the second command is defined by the information about the encoding result; and thereafter,
writing at least one of the encoding result and the original data from the RAM to the nonvolatile memory device in response to the second host command,
wherein the second host command comprises storage location information for target data selected in the host system according to a data compression rate from among the encoding result and the original data, size information for the target data, and logical address information to be mapped to the target data.

2. The method of claim 1 , wherein the storing of the original data comprises writing the original data into a storage area of the RAM, the storage area supporting a compression function or an encryption function.

3. The method of claim 1 , wherein the encoding of the original data comprises at least one of selecting one of multiple compression engines in the memory system to compress the original data, and selecting one of multiple encryption engines in the memory system to encrypt the original data based on the first host command.

4. The method of claim 1 , wherein the first host command is a first A host command, and the encoding of the original data comprises:
storing the original data in a first A address area of the RAM in response to the first A host command;
reading the original data stored in the first A address area and compressing the read original data to generate compressed data; and thereafter,
storing the compressed data in an address area of the RAM different from the first A address area.

5. The method of claim 1 , wherein the first host command is a first B host command, and the encoding of the original data comprises:
storing the original data in a first B address area of the RAM in response to the first B host command;
reading the original data stored in the first B address area and encrypting the read original data to generate encrypted data; and thereafter,
storing the encrypted data in an address area of the RAM different from the first B address area.

6. The method of claim 1 , wherein the first host command is a first C host command, and the encoding of the original data comprises:
storing the original data in a first C address area of the RAM in response to the first C host command;
reading the original data stored in the first C address area and compressing the read original data to generate compressed data;
storing the compressed data in a first B address area of the RAM different from the first C address area;
reading the compressed data stored in the first B address area and encrypting the read compressed data to generate encrypted compressed data; and
storing the encrypted compressed data in a second address area of the RAM different from the first C address area and the first B address area.

7. The method of claim 1 , wherein the writing of the at least one of the encoding result and the original data to the nonvolatile memory device comprises:
receiving the second host command comprising storage location information for target data stored in the RAM, size information for the target data, and logical address information to be mapped to the target data;
converting the logical address information into physical address information;
reading target data from the RAM based on the storage location information for the target data; and
writing the read target data to a storage location of the nonvolatile memory device that corresponds to the physical address information.

8. The method of claim 1 , wherein the information about the encoding result, includes location information and size information for the at least one of the encoding result and the original data stored in the RAM.

9. A memory system comprising:
a nonvolatile memory device; and
a memory controller that performs an operation of writing or reading data to or from the nonvolatile memory device, wherein the memory controller comprises:
a random access memory (RAM) comprising a first address area supporting an encoding function and a second address area storing an encoded result produced h the encoding function;
an encoder that encodes data stored in the first address area to produce the encoded result; and
a processor configured, in response to a first host command received from a host system, to:
(1) store original data received from the host system in the first address area of the RAM,
(2) control operation of the encoder to produce the encoded result and store the encoded result in the RAM;
(3) generate information about the encoding result, and
(4) control transmission of the information about the encoding result to the host system; and

the processor is further configured, in response to a second host command received from the host system after the producing of the encoded result, to:
(5) read target data from the RAM selected from among at least one of the encoding result and the original data, and
(6) write the target data to the nonvolatile memory device, wherein the second host command is generated by the host system based on the information about the encoded result received from the memory system and includes a logical address corresponding to the nonvolatile memory device, and

wherein the second host command comprises storage location information for the target data selected in the host system according to a data compression rate from among the encoding result and the original data, size information for the target data, and logical address information to be mapped to the target data.

10. The memory system of claim 9 , wherein the second host command is transmitted from the host system based on the information about the encoding result, and the information about the encoding result includes storage location information and size information for at least one of the original data and the encoding result stored in the RAM.

11. The memory system of claim 9 , wherein the processor generates the information about the encoding result which comprises storage location information and size information for target data selected from among the encoding result and original data stored in the RAM, based on a compression rate for the original data according to a compression process of the encoder, determines the encoding result as the target data where the compression rate is greater than or equal to a first threshold value, and determines the original data as the target data where the compression rate is less than the first threshold value.

12. The memory system of claim 9 , wherein the encoder comprises one or more compression engines for compressing data or one or more encryption engines for encrypting data, and selects one of the one or more compression engines or one of the one or more encryption engines to compress or encrypt the data stored in the first address area, based on the first host command.

13. The memory system of claim 9 , wherein the first address area comprises a first A address area supporting a compression function and a first B address area supporting an encryption function, and
the processor selectively stores the original data in o

Assignees

• Seo Man Keun
• Kim Kwang Hoon
• Jeong Sang Kyoo
• Samsung Electronics Co Ltd

Inventors

• Seo Man Keun
• Kim Kwang Hoon
• Jeong Sang Kyoo

Classifications

• G06F12/1408 Primary

  by using cryptography (for digital transmission H04L9/00) · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0623

  in relation to content · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0622

  in relation to access · CPC title