Methods and apparatus to improve turbo performance for events handling

Patent metadata

Field	Value
Publication number	US-9904346-B2
Application number	US-201514716326-A
Country	US
Kind code	B2
Filing date	May 19, 2015
Priority date	Dec 3, 2009
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.

First claim

What is claimed is:

1. A multi-core processor for executing a task, comprising:
a plurality of processing cores;
turbo mode logic to control the plurality of processing cores such that an active processing core transitions into a turbo mode by operating at a higher frequency while an idle processing core remains idle;
performance computing logic to calculate potential performance losses associated with selecting among the plurality of processing cores for handling an event, wherein said potential performance losses comprise an active performance loss (APL) for selecting the active processing core to handle the event and a waking performance loss (WPL) for selecting the idle processing core to handle the event, wherein the APL is based on a ratio of a time period for executing the task and a total runtime of both the task and a program workload being executed by the active processing core; and
task routing logic to select between the active processing core and the idle processing core for executing a task to handle the event, said selection based on a comparison between the APL and the WPL, wherein power is channeled to wake up the idle processing core unless the comparison indicates that the APL is less than the WPL.

2. The multi-core processor of claim 1 , wherein the active processing core in a turbo mode transitions to a lower operating frequency so that the power can be channeled to wake up the idle processing core.

3. The multi-core processor of claim 1 , wherein the WPL is based on a decrease of an operating frequency associated with active processing core and a frequency scalability factor of a program being executed by the active processing core.

4. The multi-core processor of claim 1 , further comprising:
memory, coupled to the performance computing logic, to hold information about a frequency scalability factor of a program being executed by the active processing core.

5. The multi-core processor of claim 1 , wherein the task is executable by any of the plurality of processing cores to handle a re-routable event.

6. A method for improving turbo performance, comprising:
transitioning an active processing core of a plurality of processing cores into a turbo mode by operating at a higher frequency while an idle processing core of the plurality of processing elements remains idle;
calculating potential performance losses associated with the plurality of processing cores handling an event, wherein an active performance loss (APL) is calculated based on a ratio of a time period for executing the task and a total runtime of both the task and a program workload being executed by the active processing core;
selecting between the active processing core and the idle processing core for executing a task to handle the event, said selection based on a comparison of the APL for selecting the active processing core to execute the task and a waking performance loss (WPL) for selecting the idle processing core to execute the task; and
channeling power to wake up the idle processing core unless the comparison indicates that the APL is less than the WPL.

7. The method of claim 6 , further comprising calculating the WPL based on a decrease of an operating frequency associated with the active processing core in the turbo mode and a frequency scalability factor of a program being executed by the active processing core.

8. The method of claim 6 , further comprising transitioning the active processing core in the turbo mode to a lower operating frequency so that the power can be channeled to wake up the idle processing core.

9. A system for improving turbo performance, comprising:
a plurality of processing cores;
turbo mode logic to control the plurality of processing cores such that an active processing core may transition into a turbo mode by operating at a higher frequency if an idle processing element remains idle;
performance computing logic to calculate potential performance losses associated with selecting among the plurality of processing cores for handling an event, wherein said potential performance losses comprise an active performance loss (APL) for selecting the active processing core to handle the event and a waking performance loss (WPL) for selecting the idle processing core to handle the event, wherein the APL is based on a ratio of a time period for executing the task and a total runtime of both the task and a program workload being executed by the active processing core;
task routing logic to select between the active processing core and the idle processing core for executing a task to handle the event, said selection based on a comparison between the APL and the WPL, wherein power is channeled to wake up the idle processing core unless the comparison indicates that the APL is less than the WPL; and
a memory, coupled to the task routing logic, to hold a frequency scalability factor of a program to be executed by one or more of the plurality of processing cores.

10. The system of claim 9 , wherein the WPL is based on a decrease of an operating frequency associated with active processing core and the frequency scalability factor of said program while it is being executed by the active processing core.

11. The system of claim 9 , wherein the active processing core in a turbo mode transitions to a lower operating frequency so that the power can be channeled to wake up the idle processing core.

12. The system of claim 9 , wherein the task is executable by any of the plurality of processing cores to handle a re-routable event.

Assignees

• Intel Corp

Inventors

• Wells Ryan D
• Falik Ohad
• Allarey Jose P

Classifications

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• Y02B60/1282

  Cross-Sectional Technologies · mapped topic

• G06F1/3296

  by lowering the supply or operating voltage · CPC title