Array substrate, display panel and display method thereof, display device

US9904089B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9904089-B2
Application numberUS-201414425991-A
CountryUS
Kind codeB2
Filing dateMay 23, 2014
Priority dateDec 30, 2013
Publication dateFeb 27, 2018
Grant dateFeb 27, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention provides an array substrate, a display panel and a display method thereof, as well as a display device. The array substrate of the present invention comprises data lines and gate lines formed on a substrate, the data lines and the gate lines are provided intersecting with and insulating from each other and define a plurality of pixel units, each of which comprises: a storage capacitor and a first thin film transistor, a gate of the first thin film transistor is connected to the corresponding gate line, a source thereof is connected to the corresponding data line, and a drain thereof is connected to one end of the storage capacitor, wherein, touch-control units are provided in at least a part of the pixel units.

First claim

Opening claim text (preview).

The invention claimed is: 1. An array substrate, comprising data lines and gate lines formed on a substrate, wherein, the data lines and the gate lines are provided intersecting with and insulating from each other and define a plurality of pixel units, each of which comprises: a storage capacitor and a first thin film transistor, a gate of the first thin film transistor is connected to the corresponding gate line, a source thereof is connected to the corresponding data line, a drain thereof is connected to one end of the storage capacitor, touch-control units are provided in only a part of the pixel units, each touch-control unit is provided in one of the pixel units and in two adjacent rows of the pixel units defined by a first gate line, a second gate line and a third gate line which are sequentially arranged, only one row of the pixel units are provided with the touch-control units therein, wherein the array substrate further comprises sensing lines and signal lines, wherein each touch-control unit comprises: a second thin film transistor and a third thin film transistor, and in each pixel unit provided with the touch-control unit, a gate of the second thin film transistor is connected to the first gate line, a drain thereof is connected to the signal line, and a source thereof is connected to the drain of the first thin film transistor; a gate of the third thin film transistor is connected to the second gate line, a source thereof is connected to a processor through the sensing line, and a drain thereof is connected to the drain of the first thin film transistor; and the gate of the first thin film transistor is connected to the third gate line. 2. The array substrate according to claim 1 , wherein, an amplifier is provided between the sensing line and the processor, an input terminal of the amplifier is connected to the sensing line, an output terminal thereof is connected to the processor, and the amplifier is used for amplifying an electrical signal received by the sensing line. 3. The array substrate according to claim 2 , wherein, the touch-control units provided in the pixel units in a same column are connected to a same sensing line. 4. The array substrate according to claim 3 , wherein, the touch-control units provided in the pixel units in a same column are connected to a same signal line. 5. The array substrate according to claim 1 , wherein, the touch-control units provided in the pixel units in a same column are connected to a same sensing line. 6. The array substrate according to claim 5 , wherein, the touch-control units provided in the pixel units in a same column are connected to a same signal line. 7. A display method of a display panel, the display panel comprising the array substrate according to claim 1 , and the display method comprising: in a touch-control phase, providing touch-control driving signals to the touch-control units, so as to determine a position of a touch point; and in a display phase, providing grayscale signals to the array substrate, so as to enable the pixel units to display. 8. The display method according to claim 7 , wherein, in the display panel, in two adjacent rows of the pixel units defined by a first gate line, a second gate line and a third gate line which are sequentially arranged, one row of the pixel units are provided with the touch-control units therein, and the display panel further comprises sensing lines and signal lines, wherein the touch-control unit comprises: a second thin film transistor and a third thin film transistor, and in each pixel unit provided with the touch-control unit, a gate of the second thin film transistor is connected to the first gate line, a drain thereof is connected to the signal line, and a source thereof is connected to the drain of the first thin film transistor; a gate of the third thin film transistor is connected to the second gate line, a source thereof is connected to a processor through the sensing line, and a drain thereof is connected to the drain of the first thin film transistor; and the gate of the first thin film transistor is connected to the third gate line, and the display method specifically comprises: in the touch-control phase, inputting a scanning signal through the first gate line to turn on the second thin film transistor, so that the storage capacitor in the pixel unit in which the touch-control unit is provided is charged through the signal line; inputting a scanning signal through the second gate line to turn on the third thin film transistor, so that the storage capacitor in the pixel unit in which the touch-control unit is provided discharges and information of a charge quantity is transferred to the processor; and in the display phase, inputting a scanning signal through the third gate line to turn on the first thin film transistor, and inputting a grayscale signal through the data line to drive the pixel unit to display. 9. A display panel, comprising an array substrate, which comprises data lines and gate lines formed on a substrate, wherein, the data lines and the gate lines are provided intersecting with and insulating from each other and define a plurality of pixel units, each of which comprises: a storage capacitor and a first thin film transistor, a gate of the first thin film transistor is connected to the corresponding gate line, a source thereof is connected to the corresponding data line, a drain thereof is connected to one end of the storage capacitor, touch-control units are provided in only a part of the pixel units, each touch-control unit is provided in one of the pixel units and in two adjacent rows of the pixel units defined by a first gate line, a second gate line and a third gate line which are sequentially arranged, only one row of the pixel units are provided with the touch-control units therein, wherein the array substrate further comprises sensing lines and signal lines, wherein each touch-control unit comprises: a second thin film transistor and a third thin film transistor, and in each pixel unit provided with the touch-control unit, a gate of the second thin film transistor is connected to the first gate line, a drain thereof is connected to the signal line, and a source thereof is connected to the drain of the first thin film transistor; a gate of the third thin film transistor is connected to the second gate line, a source thereof is connected to a processor through the sensing line, and a drain thereof is connected to the drain of the first thin film transistor; and the gate of the first thin film transistor is connected to the third gate line. 10. The display panel according to claim 9 , wherein, an amplifier is provided between the sensing line and the processor, an input terminal of the amplifier is connected to the sensing line, an output terminal thereof is connected to the processor, and the amplifier is used for amplifying an electrical signal received by the sensing line. 11. The display panel according to claim 10 , wherein, the touch-control units provided in the pixel units in a same column are connected to a same sensing line. 12. The display panel according to claim 11 , wherein, the touch-control units provided in the pixel units in a same column are connected to a same signal line. 13. The display panel according to claim 9 , wherein, the touch-control units provided in the pixel units in a same column are connected to a same sensing line. 14. The display panel according to claim 13 , wherein, the touch-control units provided in the pixel units in a same column are connected to a same signal line.

Assignees

Inventors

Classifications

  • in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

  • Control or interface arrangements specially adapted for digitisers · CPC title

  • Storage capacitors associated with the pixel electrode · CPC title

  • Input devices, e.g. touch panels · CPC title

  • Digitisers structurally integrated in a display · CPC title

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What does patent US9904089B2 cover?
The present invention provides an array substrate, a display panel and a display method thereof, as well as a display device. The array substrate of the present invention comprises data lines and gate lines formed on a substrate, the data lines and the gate lines are provided intersecting with and insulating from each other and define a plurality of pixel units, each of which comprises: a stora…
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Hefei Boe Optoelectronics Tech
What technology area does this patent fall under?
Primary CPC classification G02F1/13338. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 27 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).