Method for forming a microelectromechanical device

Patent metadata

Field	Value
Publication number	US-9902612-B2
Application number	US-201715629834-A
Country	US
Kind code	B2
Filing date	Jun 22, 2017
Priority date	Feb 26, 2016
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A method for forming a microelectromechanical device may provide forming a first layer at least one of in or over a semiconductor carrier; forming a second layer at least one of in or over at least a central region of the first layer, such that a peripheral region of the first layer is at least partially free of the second layer; removing material under at least a central region of the second layer to release at least one of the central region of the second layer or a central region of the first layer; and/or removing material under at least the peripheral region of the first layer to such that the second layer is supported by the semiconductor carrier via the first layer.

First claim

What is claimed is:

1. A method for forming a microelectromechanical device, the method comprising:
forming a first layer at least one of in or over a semiconductor carrier;
forming a second layer at least one of under or over at least a central region of the first layer, such that a peripheral region of the first layer is at least partially free of the second layer;
removing material under at least a central region of the second layer to release at least one of the central region of the second layer or a central region of the first layer; and/or
removing material under at least the peripheral region of the first layer to such that the second layer is supported by the semiconductor carrier via the first layer.

2. The method of claim 1 , further comprising:
structuring the peripheral region of the first layer to form one or more spring arms, wherein the removing material under at least the peripheral region of the first layer comprises releasing the one or more spring arms.

3. The method of claim 1 , further comprising:
forming a hollow between the first layer and the second layer.

4. The method of claim 1 , further comprising:
forming a third layer at least one of under or over the first layer between the peripheral region of the first layer and the central region of the first layer for providing a stiffening element, such that the peripheral region of the first layer and the central region of the first layer are at least partially free of the third layer.

5. The method of claim 1 ,
wherein removing material under at least the central region of the second layer comprises at least one of:
removing at least material of the semiconductor carrier; or
removing at least material of the first layer, wherein the first layer at least partially remains at least one of coupled to and under a peripheral region of the second layer.

6. The method of claim 1 ,
wherein removing material under at least the central region of the second layer comprises forming an opening under the second layer.

7. The method of claim 1 , further comprising
forming an electrically conductive layer which comprises at least one contact pad and at least one electrical member for coupling the second layer with the at least one contact pad.

8. The method of claim 1 , further comprising:
forming a first insulation layer between the first layer and the semiconductor carrier;
wherein removing material under at least a central region of the second layer comprises:
etching the semiconductor carrier with a first etchant; and/or
etching the first layer with a second etchant;

wherein the first insulation layer is used as an etch stop for the first etchant.

9. The method of claim 1 , further comprising:
forming a second insulation layer between the first layer and the second layer;
wherein removing material under at least a central region of the second layer comprises:
etching the semiconductor carrier with a first etchant; and/or
etching the first layer with a second etchant;

wherein the second insulation layer is used as an etch stop for the second etchant.

Assignees

• Infineon Technologies Ag

Inventors

• Dehe Alfons
• Barzen Stefan
• Krumbein Ulrich
• Friza Wolfgang
• Klein Wolfgang

Classifications

• B81C1/00325

  for reducing stress inside of the package structure · CPC title

• B81B3/0072 Primary

  For controlling internal stress or strain in moving or flexible elements, e.g. stress compensating layers · CPC title

• B81B2203/0109

  Bridges · CPC title

• B81C1/00301

  Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias · CPC title

• B81C1/00261

  Processes for packaging MEMS devices (MEMS packages B81B7/0032, packaging of smart-MEMS B81C1/0023) · CPC title