Protective layering process for circuit board EMI sheilding and thermal management

Patent metadata

Field	Value
Publication number	US-9900988-B1
Application number	US-201414249540-A
Country	US
Kind code	B1
Filing date	Apr 10, 2014
Priority date	Nov 28, 2011
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A protective layering process that encapsulates and protects printed circuit board assemblies with complex and imprecise geometries. The protective layering process provides a combination of a flexible mold and/or a rigid mold, which are derived from modified data from a 3 dimensional scan of the printed circuit board assembly, and which applies close-forming, encapsulating polymer layers, electrically non-conductive layers, EMI shielding layers, and/or thermal management layers to the electronic components and circuit board assemblies. Polymer layers and protective jackets are shaped to as-populated circuit boards and assemblies, providing tightly fit barriers with fine resolution accommodating imprecise geometries. The protective jackets/layers can be formed in rigid, semi-rigid, or highly flexible polymer films, to protect the circuitry from the elements, CTE mismatches, shock and vibration loads and extreme g-forces, and from internal and external EMI and to manage thermal dissipation. Multiple, nesting layers, each with different protective properties, can be formed and applied.

First claim

What is claimed is:

1. A method for encapsulating a populated circuit board assembly having an imprecise geometry, with at least one protective layer that is tightly fit to the imprecise geometry of the populated circuit board assembly, the method comprising:
making a mold of the populated circuit board assembly;
using the mold to encapsulate the populated circuit board assembly with said at least one protective layer;
wherein making the mold includes:
scanning the populated circuit board assembly to create a surface file of the populated circuit board assembly;
wherein said populated circuit board assembly includes at least one circuit board component of a component type, for which component type, the physical features, and dimensional tolerances of said a circuit board component are known;
modifying the surface file to allow for said dimensional tolerances of said component type;
using the modified surface file to create a mold;

wherein encapsulating the populated circuit board assembly with said at least one protective layer includes:
heating a first protective layer of said at least one protective layer;
drawing the heated first protective layer over and past the positive mold, in order to form an envelope with a substantially precise representation of the populated circuit board assembly;
releasing the envelope from the positive mold; and
placing the formed envelope onto the populated circuit board assembly to be encapsulated.

2. Method of claim 1 , wherein making the mold further comprises:
wherein said circuit board component has at least one substantially vertical surface which is substantially perpendicular to the populated circuit board assembly;
wherein said surface file has a substantially vertical feature corresponding to said substantially vertical surface
modifying the surface file to cant the said substantially vertical feature at a draft angle.

3. Method of claim 1 , wherein making the mold further comprises:
wherein said surface file includes at least one concavity associated with a physical feature of said component type;
further modifying the surface file to remove said concavity.

4. Method of claim 3 , wherein said physical feature is an undercut between said component type and said populated circuit board assembly.

5. Method of claim 3 , wherein said physical feature is a chip lead valley between a plurality of chip leads extending from said component type to said populated circuit board assembly.

6. Method of claim 3 , wherein said physical feature is a step or a chamfer on said component type.

7. Method of claim 3 , wherein said physical feature is a gap or a groove in the component type.

8. A method for encapsulating a populated circuit board assembly having an imprecise geometry, with at least a first protective layer that is tightly fit to the imprecise geometry of the populated circuit board assembly, the method comprising:
making a first mold of the populated circuit board assembly;
using the mold to encapsulate the populated circuit board assembly with said first protective layer;
making at least one additional mold;
using the additional mold to further encapsulate the populated circuit board with an additional layer;
wherein making the first mold includes;
scanning the populated circuit board assembly to create an initial surface file of the populated circuit board assembly;
wherein said populated circuit board assembly includes at least one circuit board component of a component type, for which component type, the physical features, and dimensional tolerances of said a circuit board component are known;
modifying the surface the to allow for said dimensional tolerances of said component type;
using the initial surface file to create a first positive mold;
wherein encapsulating the populated circuit board assembly with said first protective layer includes;
heating said first protective layer;
wherein said first protective layer is electrically insulative, it of a soft physical property similar to rubber or elastomer, has a thickness; and a top surface which is not in contact with the populated circuit board;
drawing the heated first protective layer over and past the first positive mold, in order to form a first envelope with a substantially precise representation of the populated circuit board assembly;
releasing the first envelope from the first positive mold; and
placing the formed first envelope onto the populated circuit board;
wherein making said at least one additional mold includes:
creating an additional surface file by offsetting the initial surface file by substantially the thickness of the first protective layer;
using the additional surface file to create an additional positive mold;
wherein encapsulating the populated circuit board assembly with said additional layer includes:
heating said additional layer;
drawing the heated additional layer over and past the additional positive mold, in order to form an additional formed envelope with a substantially precise representation of the top surface of the first formed envelope;
releasing the additional envelope from the additional positive mold; and
placing the additional formed envelope onto said top surface of said first formed envelope layer.

9. The method according to claim 8 , wherein the additional layer is an EMI shielding layer.

10. The method according to claim 9 , wherein the EMI shielding layer is comprised of a polymer layer with a metal filler.

11. The method according to claim 9 , wherein the EMI shielding layer is comprised of a polymer layer which is plated on at least one side with an EMI shielding coating.

12. The method according to claim 8 , wherein the additional layer is a thermally conductive layer.

Assignees

• Chao Nien Hua
• Dispenza John A
• Deangelis Mario
• Us Army

Inventors

• Chao Nien Hua
• Dispenza John A
• Deangelis Mario

Classifications

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10W74/016 Primary

  using moulds · CPC title

• B29C51/16

  Lining or labelling · CPC title

• H05K1/185 Primary

  associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards · CPC title

• H05K3/0014

  Shaping of the substrate, e.g. by moulding · CPC title