Chip aware thermal policy

Patent metadata

Field	Value
Publication number	US-9900424-B2
Application number	US-201615097429-A
Country	US
Kind code	B2
Filing date	Apr 13, 2016
Priority date	Apr 13, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Methods and apparatus are provided for chip aware thermal policies. The thermal performance mapping information is generated. The process obtains a set of process-dependent power data for each process corner of a semiconductor chip, profiles performance data, and selects an operating thermal policy based on the performance data. The thermal policy, based on the process-dependent power data is a mapping formula, or a combination of a mapping formula and a mapping table. The chip aware thermal control is based on process-dependent power data of process corners. The mapping information of process-dependent power data to a corresponding thermal policy is stored in a memory. A thermal policy is applied based on the stored mapping information and an obtained process corner information. The mapping information is applied every time the thermal policy is needed or at boot-up time.

First claim

What is claimed is:

1. A method, comprising:
obtaining a set of process-dependent power data for each process corner of a semiconductor chip;
profiling performance data based on the set of process dependent power data, a maximum temperature value, and different thermal policies; and
selecting an operating thermal policy based on the performance data such that a thermal-performance score meets a predefined criterion, wherein the thermal policy is a mapping table based on the process-dependent power data, and wherein the mapping table contains thermal policies corresponding with pairs of a process corner and a leakage.

2. The method of claim 1 , wherein the thermal policy further comprises a mapping formula.

3. The method of claim 1 , wherein the profiling performance number involves:
running all configurations for each process corner using different thermal policies;
filtering out performance data that does not meet a predefined thermal requirement; and
selecting a configuration based on the performance data, wherein the selected configuration corresponds to an entry in the policy.

4. A method, comprising:
storing mapping information of process-dependent power data to a corresponding thermal policy in a memory by a semiconductor chip;
obtaining process-dependent power data of the chip based on process corner information of the chip; and
applying a thermal policy based on the stored mapping information and the obtained process corner information, wherein the thermal policy comprises a plurality of trip temperature thresholds and corresponding thermal cooler configuration, wherein the thermal cooler configuration is applied when a detected temperature is higher than a trip temperature threshold.

5. The method of claim 4 , wherein the mapping information is a mapping table contains thermal policies corresponding with pairs of a process corner and a leakage.

6. The method of claim 4 , wherein the mapping information a mapping formula based on the process-dependent power data.

7. The method of claim 4 , wherein the mapping information is applied at boot time.

8. The method of claim 4 , wherein the mapping information is applied every time a thermal policy is needed.

9. The method of claim 4 , wherein the thermal cooler configuration comprises at least one thermal actions comprising setting a frequency limit, and setting a CPU core limit.

10. The method of claim 4 , wherein the thermal policy controls a power budget based a target temperature.

11. An apparatus, comprising:
a memory that stores mapping information of process-dependent power data to a corresponding thermal policy;
a process corner handler that obtains process-dependent power data of the chip based on process corner information of the chip; and
a thermal manager that applies a thermal policy based on the stored mapping information and the obtained process corner information, wherein the thermal policy comprises a plurality of trip temperature thresholds and corresponding thermal cooler configuration, wherein the thermal cooler configuration is applied when a detected temperature is higher than a trip temperature threshold.

12. The apparatus of claim 11 , wherein the mapping information is a mapping table contains thermal policies corresponding with pairs of a process corner and a leakage.

13. The apparatus of claim 11 , wherein the mapping information is a mapping formula based on the process-dependent power data.

14. The apparatus of claim 11 , wherein the mapping information is applied at boot time.

15. The apparatus of claim 11 , wherein the mapping information is applied every time a thermal policy is needed.

16. The apparatus of claim 11 , wherein the thermal cooler configuration comprises at least one thermal actions comprising setting a frequency limit, and setting a CPU core limit.

17. The apparatus of claim 11 , wherein the thermal policy controls a power budget based a target temperature.

18. A method, comprising:
storing mapping information of process-dependent power data to a corresponding thermal policy in a memory by a semiconductor chip;
obtaining process-dependent power data of the chip based on process corner information of the chip; and
applying a thermal policy based on the stored mapping information and the obtained process corner information, wherein the mapping information is a mapping table contains thermal policies corresponding with pairs of a process corner and a leakage.

19. An apparatus, comprising:
a memory that stores mapping information of process-dependent power data to a corresponding thermal policy;
a process corner handler that obtains process-dependent power data of the chip based on process corner information of the chip; and
a thermal manager that applies a thermal policy based on the stored mapping information and the obtained process corner information, wherein the mapping information is a mapping table contains thermal policies corresponding with pairs of a process corner and a leakage.

Assignees

• Mediatek Inc

Inventors

• Wang wei ting
• Li Han Lin
• Huang hong jie

Classifications

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G05D23/20 Primary

  with sensing elements having variation of electric or magnetic properties with change of temperature (G05D23/13 takes precedence) · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/206 Primary

  comprising thermal management · CPC title