Multi-modulus divider with power-of-2 boundary condition support

Patent metadata

Field	Value
Publication number	US-9900012-B2
Application number	US-201615099753-A
Country	US
Kind code	B2
Filing date	Apr 15, 2016
Priority date	Apr 16, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.

First claim

What is claimed is:

1. A frequency divider circuit comprising:
a plurality of flip-flops operatively coupled to carry out division of an input frequency, the plurality of flip-flops configured to generate a modulus output and to receive a divided clock signal of a previous cell; and
an additional flip-flop that is selectively clocked off the modulus output or the divided clock of the previous stage, depending at least in part on a control signal applied to a data input of the additional flip-flop, wherein the additional flip-flop is configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.

2. The circuit of claim 1 wherein the correct divide ratio is all zeros.

3. The circuit of claim 1 wherein the control signal applied to the data input of the additional flip-flop has a first state that causes the additional flip-flop to be clocked off the modulus output, and the first state occurs in response to modulus control changing before a given divide cycle is complete.

4. The circuit of claim 1 wherein the additional flip-flop resets the plurality of flip-flops in response to an incorrect division occurring due to a power-of-2 boundary crossing.

5. The circuit of claim 1 wherein the plurality of flip-flops is configured as a divide-by-2-or-3 cell.

6. The circuit of claim 1 wherein the plurality of flip-flops is configured as a divide-by-1-or-2-or-3 cell.

7. The circuit of claim 1 wherein the additional flip-flop is part of a reset circuit that further includes a multiplexer, the multiplexer having an output coupled to a clock input of the additional flip-flop, and a select/control coupled to an output of the additional flip-flop, wherein a first input of the multiplexer is coupled to the modulus output and a second input of the multiplexer is coupled to the divided clock signal of a previous cell.

8. The circuit of claim 7 wherein the reset circuit further includes a two-input OR-gate having its first input coupled to the modulus output and its second output coupled to the output of the additional flip-flop, and the modulus output is represented at an output of the OR-gate.

9. A frequency divider circuit comprising:
a plurality of D-type flip-flops operatively coupled as a divide-by-2-or-3 cell to carry out division of an input frequency, the plurality of D-type flip-flops configured to generate a modulus output and to receive a divided clock signal of a previous cell; and
an additional D-type flip-flop that is selectively clocked off the modulus output or the divided clock of the previous stage, depending at least in part on a control signal applied to a data input of the additional D-type flip-flop, wherein the additional D-type flip-flop is configured to selectively reset the plurality of D-type flip-flops to a state that will result in a correct divide ratio.

10. The circuit of claim 9 wherein the correct divide ratio is all zeros.

11. The circuit of claim 9 wherein the control signal applied to the data input of the additional D-type flip-flop has a first state that causes the additional D-type flip-flop to be clocked off the modulus output, and the first state occurs in response to modulus control changing before a given divide cycle is complete.

12. The circuit of claim 9 wherein the additional D-type flip-flop resets the plurality of D-type flip-flops in response to an incorrect division occurring due to a power-of-2 boundary crossing.

13. The circuit of claim 9 wherein the additional D-type flip-flop is part of a reset circuit that further includes a two-input multiplexer, the two-input multiplexer having an output coupled to a clock input of the additional D-type flip-flop, and a select/control coupled to an output of the additional D-type flip-flop, wherein a first input of the two-input multiplexer is coupled to the modulus output and the second input of the two-input multiplexer is coupled to the divided clock signal of a previous cell.

14. The circuit of claim 13 wherein the reset circuit further includes a two-input OR-gate having its first input coupled to the modulus output and its second output coupled to the output of the additional D-type flip-flop, and the modulus output is represented at an output of the OR-gate.

15. A frequency divider circuit comprising:
a plurality of D-type flip-flops operatively coupled as a divide-by-1-or-2-or-3 cell to carry out division of an input frequency, the plurality of D-type flip-flops configured to generate a modulus output and to receive a divided clock signal of a previous cell; and
an additional flip-flop that is selectively clocked off the modulus output or the divided clock of the previous stage, depending at least in part on a control signal applied to a data input of the additional flip-flop, wherein the additional flip-flop is configured to selectively reset the plurality of D-type flip-flops to a state that will result in a correct divide ratio.

16. The circuit of claim 15 wherein the correct divide ratio is all zeros.

17. The circuit of claim 15 wherein the control signal applied to the data input of the additional flip-flop has a first state that causes the additional flip-flop to be clocked off the modulus output, and the first state occurs in response to modulus control changing before a given divide cycle is complete.

18. The circuit of claim 15 wherein the additional flip-flop resets the plurality of D-type flip-flops in response to an incorrect division occurring due to a power-of-2 boundary crossing.

19. The circuit of claim 15 wherein the additional flip-flop is part of a reset circuit that further includes a two-input multiplexer, the two-input multiplexer having an output coupled to a clock input of the additional flip-flop, and a select/control coupled to an output of the additional flip-flop, wherein a first input of the two-input multiplexer is coupled to the modulus output and the second input of the two-input multiplexer is coupled to the divided clock signal of a previous cell.

20. The circuit of claim 19 wherein the reset circuit further includes a two-input OR-gate having its first input coupled to the modulus output and its second output coupled to the output of the additional flip-flop, and the modulus output is represented at an output of the OR-gate.

Assignees

• Bae Sys Inf & Elect Sys Integ

Inventors

• Cali Joseph D
• Grens Curtis M
• Kushner Lawrence J
• Turner Steven E

Classifications

• H03L7/1974

  for fractional frequency division · CPC title

• H03K23/00

  Pulse counters comprising counting chains; Frequency dividers comprising counting chains (H03K29/00 takes precedence) · CPC title

• H03K21/38

  Starting, stopping or resetting the counter (counters with a base other than a power of two H03K23/48, H03K23/66) · CPC title

• G06F7/68

  using pulse rate multipliers or dividers {pulse rate multipliers or dividers per se}(G06F7/70 takes precedence {; frequency division in electronic watches G04G3/02; frequency multiplication or division in oscillators H03B19/00; frequency dividing counters per se H03K23/00 - H03K29/00}) · CPC title

• H03K23/64

  with a base or radix other than a power of two (H03K23/40 - H03K23/62 take precedence) · CPC title