High electron mobility transistor and method of forming the same

Patent metadata

Field	Value
Publication number	US-9899493-B2
Application number	US-201615377622-A
Country	US
Kind code	B2
Filing date	Dec 13, 2016
Priority date	Jan 4, 2013
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.

First claim

What is claimed is:

1. A method of forming a High Electron Mobility Transistor (HEMT), the method comprising:
epitaxially growing a first III-V compound layer having a first band gap;
epitaxially growing a second III-V compound layer having a second band gap smaller than the first band gap over the first III-V compound layer;
epitaxially growing a third III-V compound layer having a third band gap greater than the first band gap over the second III-V compound layer;
forming a dielectric passivation layer over the third III-V compound layer;
forming a gate dielectric layer, wherein the gate dielectric layer comprises a first portion extending into the dielectric passivation layer;
forming a gate electrode over the third III-V compound layer; and
forming a source region and a drain region over the third III-V compound layer and on opposite sides of the gate electrode, wherein the forming the source region and the drain region comprises:
etching both the gate dielectric layer and the dielectric passivation layer to form an opening;
filling a metal feature into the opening; and
performing an anneal so that the metal feature forms metal compounds with both the second III-V compound layer and the third III-V compound layer.

2. The method of claim 1 , wherein the second III-V compound layer is undoped or unintentionally doped during the step of epitaxially growing the second III-V compound layer.

3. The method of claim 1 , wherein the forming the dielectric passivation layer comprises:
depositing the dielectric passivation layer over and contacting the third III-V compound layer; and
patterning the dielectric passivation layer to form an opening, wherein a portion of the third III-V compound layer is exposed through the opening; and
depositing the gate dielectric layer, wherein the gate dielectric layer extends into the opening.

4. The method of claim 3 , wherein after the source region and the drain region are formed, the gate dielectric layer and the dielectric passivation layer both extend from a first side to an opposite second side of one of the source region and the drain region, and the gate dielectric layer extends continuously from the source region to the drain region.

5. The method of claim 3 , wherein portion of the gate electrode extends into the opening.

6. The method of claim 1 , wherein the epitaxially growing the first III-V compound layer comprises growing a gallium nitride (GaN) layer, the epitaxially growing the second III-V compound layer comprises growing an indium gallium nitride (InGaN) layer, and epitaxially growing the third III-V compound layer comprises growing an aluminum gallium nitride (AlGaN) layer.

7. The method of claim 1 , wherein the second III-V compound layer is grown to contact the first III-V compound layer, and the third III-V compound layer is grown to contact the second III-V compound layer.

8. A method comprising:
epitaxially growing a first III-V compound layer comprising gallium nitride over a substrate;
epitaxially growing a second III-V compound layer over the first III-V compound layer, wherein the second III-V compound layer comprises indium gallium nitride;
epitaxially growing a third III-V compound layer over the second III-V compound layer, wherein the third III-V compound layer comprises aluminum gallium nitride;
depositing a dielectric passivation layer over the third III-V compound layer;
forming a first opening in the dielectric passivation layer, with a portion of the third III-V compound layer exposed through the first opening;
depositing a dielectric layer comprising:
a first portion overlapping a portion of the dielectric passivation layer; and
a second portion extending into the dielectric passivation layer;

forming a gate electrode over and contacting the dielectric layer;
patterning both the gate dielectric and the dielectric passivation layer to form a second opening, with a portion of the third III-V compound layer exposed through the second opening;
filling a metal feature into the second opening; and
performing an anneal so that the metal feature forms metal compounds with both the second III-V compound layer and the third III-V compound layer.

9. The method of claim 8 , wherein the dielectric passivation layer laterally surrounds the metal feature, and the dielectric layer and the dielectric passivation layer both extend from a first side to an opposite second side of the metal feature.

10. The method of claim 8 , wherein the metal feature and the metal compounds form a source region, and the method further comprising forming a drain region on an opposite side of the gate electrode than the source region, and the dielectric layer extends continuously from the source region to the drain region.

11. The method of claim 8 , wherein the depositing the dielectric layer comprises depositing a single layer, wherein a lowest bottom surface of the dielectric layer is coplanar with and contacting a second portion of a planar topmost top surface of the third III-V compound layer, and the gate electrode is in contact with the single layer.

12. The method of claim 8 , wherein the first III-V compound layer has a first band gap, the second III-V compound layer has a second band gap smaller than the first band gap, and the third III-V compound layer has a third band gap greater than the first band gap.

13. The method of claim 8 , wherein the filling the metal feature is finished when a top surface of the metal feature is higher than a topmost surface of the dielectric layer.

14. The method of claim 8 , wherein the anneal is performed until the metal compounds penetrate through a Two-Dimensional Electron Gas (2DEG) formed in the second III-V compound layer.

15. A method comprising:
forming a gallium nitride (GaN) layer;
forming an indium gallium nitride (InGaN) layer over and contacting the GaN layer;
forming an aluminum gallium nitride (AlGaN) layer over and contacting the InGaN layer;
depositing a dielectric passivation layer over the AlGaN layer;
etching the dielectric passivation layer to form a first opening;
depositing a dielectric layer, wherein the dielectric layer comprises a portion overlapping and contacting the AlGaN layer, wherein a the portion of the dielectric layer forms a gate dielectric extending into the first opening, and the gate dielectric does not extend into the AlGaN layer;
forming a gate electrode over and contacting the gate dielectric;
etching both the dielectric layer and the dielectric passivation layer to form second openings;
forming a source region and a drain region extending into the second openings, wherein the source region and the drain region comprise:
metal portions over the AlGaN layer, wherein the metal portions penetrate through the dielectric passivation layer, with top portions of the metal portions higher than entireties of the dielectric passivation layer; and
inter-metallic compounds underlying and joined to respective ones of the metal portions, wherein the inter-metallic compounds extend into the AlGaN layer and the InGaN layer, wherein one of the inter-metallic compounds extends from a top surface of the AlGaN layer to a level below a bottom surface of the AlGaN layer.

16. The method of claim 15 , wherein the gate dielectric and the dielectric passivation layer both extend from a first side to an opposite second side of each of the source region and the drain region, and the gate dielectric extends continuously from the source region to the drain region.

17. The method of claim 15 , wherein the GaN layer, the InGaN layer, and the AlGa

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiang Chen Hao
• Liu Po Chun
• Chiu Han Chin
• Chen Chi Ming
• Yu Chung Yi

Classifications

• H10P14/3216

  Nitrides · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P30/208

  of electrically inactive species · CPC title