Semiconductor device

Patent metadata

Field	Value
Publication number	US-9899404-B2
Application number	US-201514957099-A
Country	US
Kind code	B2
Filing date	Dec 2, 2015
Priority date	May 29, 2012
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a first string selection gate line and a second string selection gate line on the semiconductor substrate, wherein the first and second string selection gate lines are spaced apart from each other, and wherein the first and second string selection gate lines are located at a same distance from an upper surface of the semiconductor substrate;
an isolation pattern disposed between the first and second string selection gate lines, wherein the first and second string selection gate lines comprise respective sides that face each other across the isolation pattern, and wherein the side of the first string selection gate line comprises a first portion and a second portion;
a first channel area passing through the first string selection gate line; and
a second channel area passing through the second string selection gate line;
wherein the first portion of the side of the first string selection gate line is more recessed than the second portion of the side of the first string selection gate line in a plan view.

2. The semiconductor device of claim 1 , wherein the first portion of the side of the first string selection gate line has a curved shape toward the first channel area in the plan view.

3. The semiconductor device of claim 2 , wherein the side of the second string selection gate line comprises a curve that faces the curved shape of the first portion of the side of the first string selection gate line.

4. The semiconductor device of claim 1 , further comprising:
a plurality of cell gate electrodes vertically arranged on the semiconductor substrate,
wherein the first string selection gate line is on the plurality of cell gate electrodes.

5. The semiconductor device of claim 4 , wherein the isolation pattern overlaps an uppermost cell gate electrode of the plurality of cell gate electrodes.

6. The semiconductor device of claim 1 , wherein the side of the first string selection gate line comprises a plurality of curves in the plan view.

7. The semiconductor device of claim 1 , further comprising an auxiliary pattern that contacts the isolation pattern.

8. A semiconductor device comprising:
a semiconductor substrate;
a first string selection gate electrode and a second string selection gate electrode on the semiconductor substrate, wherein the first and second string selection gate electrodes are separated from each other, wherein the first and second string selection gate electrodes are located at a same distance from an upper surface of the semiconductor substrate, wherein the first and second string selection gate electrodes comprise respective sides that face each other, and wherein the side of the first string selection gate electrode has a curved shape in a plan view;
a first channel area passing through the first string selection gate electrode; and
a second channel area passing through the second string selection gate electrode.

9. The semiconductor device of claim 8 , wherein the curved shape of the side of the first string selection gate electrode reduces a width of the first string selection gate electrode in the plan view.

10. The semiconductor device of claim 8 , wherein the side of the second string selection gate electrode has a curved shape that faces the curved shape of the side of the first string selection gate electrode in the plan view.

11. The semiconductor device of claim 8 , wherein the curved shape of the side of the first string selection gate electrode curves inwardly toward the first channel area.

12. A semiconductor device comprising:
a semiconductor substrate;
a selection gate electrode on the semiconductor substrate, wherein the selection gate electrode comprises first and second conductive lines that are separated from one another; and
a plurality of channel areas passing through the selection gate electrode and including a first channel area, a second channel area, a third channel area, and a fourth channel area, wherein the first channel area and the third channel area pass through the first conductive line, wherein the second channel area and the fourth channel area pass through the second conductive line,
wherein the first and second conductive lines comprise respective sides that face each other, and
wherein the side of the first conductive line between the first channel area and the second channel area has a curved shape in a plan view.

13. The semiconductor device of claim 12 , wherein the side of the second conductive line of the selection gate electrode has a curved shape that faces the curved shape of the side of the first conductive line in the plan view.

14. The semiconductor device of claim 12 , further comprising an isolation pattern between the first and second conductive lines of the selection gate electrode.

15. The semiconductor device of claim 14 , wherein the first and second conductive lines of the selection gate electrode are located at the same level as each other.

16. The semiconductor device of claim 15 , further comprising:
a plurality of conductive patterns between the first and second conductive lines and the semiconductor substrate, the plurality of conductive patterns comprising a plurality of cell gate electrodes,
wherein the isolation pattern overlaps an uppermost cell gate electrode of the plurality of cell gate electrodes.

17. The semiconductor device of claim 12 ,
wherein a width of each of the channel areas is greater than a width of a space between the first conductive line and the second conductive line.

18. The semiconductor device of claim 12 ,
wherein a distance between the first channel area and the side of the first conductive line is larger than a distance between the third channel area and the side of the first conductive line.

19. The semiconductor device of claim 12 , wherein the curved shape of the side of the first conductive line curves inwardly toward the first channel area.

Assignees

• Yoo Jin Hyuk
• Jang Dae Hyun
• Kong Yoo Chul
• Shin Kyoung Sub
• Samsung Electronics Co Ltd

Inventors

• Yoo Jin Hyuk
• Jang Dae Hyun
• Kong Yoo Chul
• Shin Kyoung Sub

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L27/11524

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic