Vertical memory devices having contact plugs contacting stacked gate electrodes

Patent metadata

Field	Value
Publication number	US-9899394-B2
Application number	US-201615001877-A
Country	US
Kind code	B2
Filing date	Jan 20, 2016
Priority date	Mar 10, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A vertical memory device includes a plurality of gate electrodes at a plurality of levels, respectively, spaced apart from each other in a vertical direction substantially perpendicular to a top surface of a substrate, a channel extending in the vertical direction on the substrate and penetrating through the gate electrodes, and a plurality of contact plugs extending in the vertical direction and contacting the gate electrodes, respectively. At least one second contact plug is formed on a first gate electrode among the plurality of gate electrodes, and extends in the vertical direction.

First claim

What is claimed is:

1. A vertical memory device, comprising:
gate electrodes at a plurality of levels, respectively, spaced apart from each other in a vertical direction substantially perpendicular to a top surface of a substrate including a memory cell region and a peripheral region, the gate electrodes being in the memory cell region of the substrate;
a channel extending in the vertical direction on the substrate and penetrating through ones of the gate electrodes; and
first contact plugs extending in the vertical direction, the first contact plugs electrically contacting the gate electrodes, respectively; and
at least one third contact plug directly on the substrate in the memory cell region adjacent to one of the gate electrodes at a lowermost level, the at least one third contact plug extending in the vertical direction only in the memory cell region of the substrate and having a top surface substantially coplanar with top surfaces of the first contact plugs, and the at least one third contact plug not contacting the one of the gate electrodes at the lowermost level.

2. The vertical memory device of claim 1 , wherein each of the gate electrodes extends in a first direction substantially parallel to the top surface of the substrate,
and wherein, in plan view, the first contact plugs and the at least one third contact plug are uniformly spaced from each other along the first direction.

3. The vertical memory device of claim 1 , wherein the gate electrodes define a staircase shape having respective lengths in a first direction substantially parallel to the top surface of the substrate, wherein the respective lengths are decreasing from a lower level of the staircase shape toward an upper level thereof,
and wherein the at least one third contact plug is disposed on a portion of the substrate adjacent the one of the gate electrodes at the lowermost level in the first direction.

4. The vertical memory device of claim 1 , further comprising first wirings contacting top surfaces of the first contact plugs, respectively,
wherein an electrical signal is applied to the first contact plugs through a second wiring in the peripheral region of the substrate.

5. The vertical memory device of claim 4 , wherein a top surface of the at least one third contact plug contacts one of the first wirings on the top surface of one of the first contact plugs contacting the one of the gate electrodes at the lowermost level such that the at least one third contact plug and the one of the first contact plugs electrically contact the one of the first wirings.

6. The vertical memory device of claim 4 , wherein the at least one third contact plug is connected to a third wiring different from the first wirings.

7. The vertical memory device of claim 4 , wherein the at least one third contact plug comprises a dummy contact plug that is free of electrical connections to wirings configured to apply electrical signals.

8. The vertical memory device of claim 1 , further comprising:
at least one second contact plug extending in the vertical direction on a first gate electrode among the gate electrodes such that the at least one second contact plug and one of the first contact plugs both electrically contact the first gate electrode, the at least one second contact plug having a top surface substantially coplanar with the top surfaces of the first contact plugs.

9. A vertical memory device, comprising:
a channel extending in a vertical direction on a substrate, the vertical direction being substantially perpendicular to a top surface of the substrate;
a charge storage structure on an outer sidewall of the channel;
gate electrodes at a plurality of levels, respectively, spaced apart from each other in the vertical direction, one or more of the gate electrodes on the charge storage structure and extending in a first direction, and the gate electrodes defining a staircase shape of which respective lengths of the gate electrodes in the first direction are decreasing from a lower level toward an upper level;
first contact plugs each extending in the vertical direction and contacting an edge portion of a corresponding one of the gate electrodes, wherein the edge portion is not overlapped by ones of the gate electrodes at upper levels; and
at least one second contact plug extending in the vertical direction on the edge portion of a first gate electrode of the gate electrodes alongside one of the first contact plugs on the edge portion of the first gate electrode such that the at least one second contact plug, the one of the first contact plugs, and the first gate electrode are electrically connected, wherein the respective lengths in the first direction of the gate electrodes sequentially stacked in the vertical direction are decreasing by a first value, while a difference between a length in the first direction of the first gate electrode and a length in the first direction of one of the gate electrodes nearest to the first gate electrode and disposed over the first gate electrode has a second value that is greater than the first value.

10. The vertical memory device of claim 9 , wherein the first contact plugs and the at least one second contact plug are uniformly spaced from each other along the first direction.

11. The vertical memory device of claim 9 , wherein a top surface of the at least one second contact plug is substantially coplanar with top surfaces of the first contact plugs.

12. The vertical memory device of claim 9 , wherein the gate electrodes include a plurality of the first gate electrodes.

13. The vertical memory device of claim 9 , wherein the first gate electrode is disposed at a lowermost level among the gate electrodes, wherein the first gate electrode is directly adjacent the top surface of the substrate.

14. A memory device, comprising:
conductive gate electrodes stacked on a substrate, wherein the conductive gate electrodes define selection lines and word lines of the memory device;
a channel structure on the substrate and extending through ones of the conductive gate electrodes; and
conductive contact plugs extending toward the substrate substantially parallel to the channel structure and onto the conductive gate electrodes,
wherein first ones of the conductive contact plugs electrically contact first ones of the conductive gate electrodes, respectively, and
wherein second ones of the conductive contact plugs extend on a second one of the conductive gate electrodes such that multiple of the second ones of the conductive contact plugs are electrically connected to one another and electrically contact the second one of the conductive gate electrodes at respective side-by-side portions of the second one of the conductive gate electrodes.

15. The memory device of claim 14 , wherein surfaces of the first and second ones of the conductive contact plugs opposite the substrate are substantially coplanar, wherein the first ones of the conductive contact plugs extend toward the substrate to different depths, and wherein the second ones of the conductive contact plugs extend toward the substrate to respective depths that are different than the different depths of the first ones of the conductive contact plugs.

16. The memory device of claim 15 , further comprising:
first wiring lines extending substantially parallel on the surfaces of the first ones of the conductive contact plugs and electrically coupled to the first ones of the conductive gate electrodes, respectively; and
a second wiring line on the surfaces of the second ones of the conductive contact plugs and electrically coupled to the second one of th

Assignees

• Hwang Sung Min
• Kim Jee Yong
• Byeon Dae Seok
• Samsung Electronics Co Ltd

Inventors

• Hwang Sung Min
• Kim Jee Yong
• Byeon Dae Seok

Classifications

• H01L27/115 Primary

  Electricity · mapped topic

• H01L27/11578

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/11563

  Electricity · mapped topic