Forming on-chip metal-insulator-semiconductor capacitor

Patent metadata

Field	Value
Publication number	US-9899372-B1
Application number	US-201615339164-A
Country	US
Kind code	B1
Filing date	Oct 31, 2016
Priority date	Oct 31, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins on a first region of the semiconductor substrate, forming a bi-polymer structure, selectively removing the first polymer of the bi-polymer structure and forming deep trenches in the semiconductor substrate resulting in pillars in a second region of the semiconductor structure. The method further includes selectively removing the second polymer of the bi-polymer structure, doping the pillars, and depositing a high-k metal gate (HKMG) over the first and second regions to form the MIS capacitor in the second region of the semiconductor substrate.

First claim

What is claimed is:

1. A method for forming a metal-insulator-semiconductor (MIS) capacitor on a semiconductor substrate, the method comprising:
forming a plurality of fins on a first region of the semiconductor substrate;
forming a bi-polymer structure;
selectively removing the first polymer of the bi-polymer structure;
forming deep trenches in the semiconductor substrate resulting in pillars in a second region of the semiconductor structure, the deep trenches filled with oxide;
selectively removing the second polymer of the bi-polymer structure;
doping the pillars; and
depositing a high-k metal gate (HKMG) over the first and second regions to form the MIS capacitor in the second region of the semiconductor substrate,
wherein the oxide is recessed to expose a top surface of the pillars in the second region of the semiconductor substrate;
wherein a first spacer is applied over the pillars and within troughs of the plurality of fins; and
wherein a first mask is applied over the plurality of fins, the first spacer is etched from the second region of the semiconductor substrate, and the oxide is removed from the troughs defined between the pillars.

2. The method of claim 1 , further comprising depositing a directed self-assembly (DSA) co-polymer to form the bi-polymer structure by anneal.

3. The method of claim 1 , wherein the first mask is stripped after doping the pillars and before depositing the HKMG over the pillars.

4. The method of claim 3 , wherein a second mask is applied and a portion of the HKMG is etched to form a recess between the first and second regions of the semiconductor substrate.

5. The method of claim 4 , wherein the second mask is stripped, the recess is filled with an oxide, the HKMG is recessed, and a second spacer is applied over exposed regions of the HKMG.

6. The method of claim 5 , wherein epitaxial growth is performed over exposed regions of the plurality of fins on the first region of the semiconductor substrate.

Assignees

• IBM

Inventors

• Bi Zhenxing
• Cheng Kangguo
• Xu Peng
• Zhang Chen

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title