Semiconductor package structure

Patent metadata

Field	Value
Publication number	US-9899305-B1
Application number	US-201715581667-A
Country	US
Kind code	B1
Filing date	Apr 28, 2017
Priority date	Apr 28, 2017
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A semiconductor package structure is disclosed. The semiconductor package structure includes: a substrate having a front surface and a back surface; a chip-on-interposer structure mounted on the front surface of the substrate; a back side stiffener mounted over the back surface of the substrate and surrounding a projection of the chip-on-interposer structure from a back surface perspective; and a plurality of conductive bumps mounted on the back surface of the substrate.

First claim

What is claimed is:

1. A semiconductor package structure, comprising:
a substrate having a front surface and a back surface;
a chip-on-interposer structure mounted on the front surface of the substrate;
a back side stiffener mounted over the back surface of the substrate and surrounding a projection of the chip-on-interposer structure from a back surface perspective; and
a plurality of conductive bumps mounted on the back surface of the substrate.

2. The semiconductor package structure of claim 1 , further comprising a front side stiffener mounted over the front surface of the substrate substantially and along four edges of the substrate.

3. The semiconductor package structure of claim 1 , wherein the back side stiffener is a tetragonal ring having four outer edges and four inner edges from the back surface perspective.

4. The semiconductor package structure of claim 3 , wherein the back side stiffener overlaps a projection of at least four edges of the chip-on-interposer structure from a back surface perspective.

5. The semiconductor package structure of claim 4 , wherein the back side stiffener includes an outer tetragonal ring portion and an inner tetragonal ring portion, the outer tetragonal ring portion not overlapping the projection of the chip-on-interposer structure, the inner tetragonal ring portion overlapping the projection of the chip-on-interposer structure, and a width of the outer tetragonal ring portion is substantially the same with a width of the inner tetragonal ring portion from the back surface perspective.

6. The semiconductor package structure of claim 3 , wherein a portion of the conductive bumps is disposed within the four inner edges of the back side stiffener.

7. The semiconductor package structure of claim 1 , wherein the back side stiffener comprises copper.

8. A semiconductor package structure, comprising:
a substrate having a front surface and a back surface;
a first semiconductor structure mounted on the front surface of the substrate;
a second semiconductor structure mounted on the front surface of the substrate;
a front side stiffener mounted over the front surface of the substrate and substantially along four edges of the substrate;
a first back side stiffener mounted over the back surface of the substrate and surrounding a projection of the first semiconductor structure from a back surface perspective;
a second back side stiffener mounted over the back surface of the substrate and surrounding a projection of the second semiconductor structure from the back surface perspective; and
a plurality of conductive bumps mounted on the back surface of the substrate.

9. The semiconductor package structure of claim 8 , wherein the first back side stiffener is a tetragonal ring having four outer edges and four inner edges from the back surface perspective; and the second back side stiffener is a tetragonal ring having four outer edges and four inner edges from the back surface perspective.

10. The semiconductor package structure of claim 9 , wherein the first back side stiffener overlaps a projection of at least four edges of the first semiconductor structure from the back surface perspective; and the second back side stiffener overlaps a projection of at least four edges of the second semiconductor structure from the back surface perspective.

11. The semiconductor package structure of claim 9 , wherein a portion of the conductive bumps is disposed within the four inner edges of the first back side stiffener and the four inner edges of the second back side stiffener.

12. The semiconductor package structure of claim 8 , wherein the back side stiffener comprises brass.

13. The semiconductor package structure of claim 8 , wherein a height of the back side stiffener is less than a height of the conductive bumps.

14. A semiconductor package structure, comprising:
a substrate having a front surface and a back surface;
a semiconductor structure mounted on the front surface of the substrate;
a back side stiffener including a tetragonal ring portion and a flat plate portion, the back side stiffener being mounted over the back surface of the substrate; and
a plurality of conductive bumps mounted on the back surface of the substrate.

15. The semiconductor package structure of claim 14 , further comprising a front side stiffener mounted over the front surface of the substrate and substantially along four edges of the substrate.

16. The semiconductor package structure of claim 14 , wherein the tetragonal ring portion has four outer edges and four inner edges from a back surface perspective, and the tetragonal ring portion overlaps a projection of at least four edges of the semiconductor structure from the back surface perspective.

17. The semiconductor package structure of claim 16 , wherein the flat plate portion covers a space defined by the four inner edges from the back surface perspective, and the back side stiffener is mounted over the back surface of the substrate through the tetragonal ring portion.

18. The semiconductor package structure of claim 14 , wherein the flat plate portion fully overlaps a projection of the semiconductor structure from the back surface perspective.

19. The semiconductor package structure of claim 14 , further comprising a passive chip component disposed over the back side of the substrate within the four inner edges of the tetragonal ring portion, a height of the passive chip component being less than a distance between the flat plate portion and the back surface of the substrate.

20. The semiconductor package structure of claim 14 , wherein the back side stiffener comprises stainless steel.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yeh Ting Yu
• Chen Wei Ming
• Sun Yi Chiang

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title