Microelectronic packages having mold-embedded traces and methods for the production thereof

Patent metadata

Field	Value
Publication number	US-9899298-B2
Application number	US-201615087640-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Mar 15, 2013
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.

First claim

What is claimed is:

1. A microelectronic package, comprising:
a molded package body;
a first semiconductor die embedded within the molded package body, the first semiconductor die having a backside and a sidewall;
a first Surface Mount Device (SMD) positioned on the backside of the first semiconductor die, embedded within the molded package body, and having a first terminal;
at least one redistribution layer overlying the molded package body and containing a first interconnect line; and
a first electrically-conducive trace further embedded within the molded package body and extending from the first interconnect line, along the sidewall of the first semiconductor die, and to the first terminal of the first SMD.

2. The microelectronic package of claim 1 wherein the first electrically-conductive trace comprises a metal-containing ink.

3. The microelectronic package of claim 1 wherein the first electrically-conductive trace comprises a vertically-extending column extending through the molded package body.

4. The microelectronic package of claim 1 wherein the first electrically-conductive trace includes an enlarged pad region in ohmic contact with the interconnect line.

5. The microelectronic package of claim 1 further comprising:
an array of SMDs in which the first SMD is included, the array of SMDs distributed across the backside of the first semiconductor die; and
a plurality of electrically-conductive traces in which the first electrically-conductive trace is included, the plurality of electrically-conductive traces interconnecting the array of SMDs.

6. The microelectronic package of claim 1 further comprising a second semiconductor die embedded in the molded package body and interconnected with the first semiconductor die through the electrically-conductive trace.

7. The microelectronic package of claim 6 wherein the first and second semiconductor die are stacked in a back-to-back relationship.

8. The microelectronic package of claim 1 further comprising a radio frequency antenna structure electrically coupled to the first semiconductor die through the first electrically-conductive trace.

9. The microelectronic package of claim 8 wherein the first electrically-conductive trace is integrally formed with the radio frequency antenna structure.

10. The microelectronic package of claim 1 wherein the first semiconductor die comprises a bond pad, and wherein the interconnect line electrically couples the bond pad to the first electrically-conductive trace.

11. The microelectronic package of claim 1 wherein the molded package body has a sidewall to which the first electrically-conductive trace extends, and wherein the microelectronic package further comprises:
a sidewall conductor located on the sidewall of the molded package body and in ohmic contact with the first electrically-conductive trace.

12. The microelectronic package of claim 1 wherein the first electrically-conductive trace comprises a cross-over region, and wherein the microelectronic package further comprises:
a second electrically-conductive trace embedded within the molded package body and extending over the cross-over region of the first electrically-conductive trace; and
dielectric material separating the cross-over region of the first electrically-conductive trace from the second electrically-conductive trace.

13. The microelectronic package of claim 1 wherein the SMD is selected from the group consisting of a discrete two terminal resistor, a discrete two terminal capacitor, a discrete two terminal indicator, and a discrete two terminal diode.

14. The microelectronic package of claim 1 wherein the first SMD further comprises a second terminal, and wherein the microelectronic package further comprises:
a second SMD positioned on the backside of the first semiconductor die at a location adjacent the first SMD; and
a second electrically-conducive trace electrically connecting a terminal of the second SMD to the second terminal of the first SMD.

15. A microelectronic package, comprising:
a semiconductor die;
a first electrically-conducive ink trace composed of a metal-containing ink and contacting the semiconductor die;
a molded package body in which the semiconductor die and the first electrically-conductive ink trace are embedded; and
at least one redistribution layer overlying the molded package body, the at least one redistribution layer containing a first interconnect line in electrical contact with the first electrically-conducive ink trace.

16. The microelectronic package of claim 15 wherein the semiconductor die has a backside, wherein the microelectronic package further comprises first and second Surface Mount Devices (SMDs) in a side-by-side relationship on the backside of the semiconductor die, and wherein the first and second SMDs are interconnected by the first electrically-conducive ink trace.

17. A microelectronic package, comprising:
a molded package body;
a semiconductor die embedded within the molded package body;
one or more redistribution layers formed over the molded package body and containing interconnect lines electrically coupled to the semiconductor die; and
printed electrically-conductive ink traces embedded within the molded package body and electrically coupled to the semiconductor die through the interconnect lines.

18. The microelectronic package of claim 17 wherein the printed electrically-conductive ink traces extend over and are conformal with one or more surfaces of the semiconductor die.

19. The microelectronic package of claim 17 further comprising a Surface Mount Device (SMD) positioned over a backside of the semiconductor die, the SMD having a first terminal electrically coupled to a first interconnect line included in the interconnect lines through a first printed electrically-conductive ink trace in the printed electrically-conductive ink traces.

20. The microelectronic package of claim 17 wherein the first printed electrically-conductive ink trace comprises:
an enlarged pad region contacting the first interconnect line;
a vertically-extending portion coupled to the enlarged pad region and extending along a sidewall of the semiconductor die; and
a horizontally-extending terminal end portion coupled to the vertically-extending portion and extending over a region of the backside of the semiconductor die to the first terminal of the SMD.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Vincent Michael B
• Gong Zhiwei
• Wright Jason R

Classifications

• B32B37/12

  characterised by using adhesives · CPC title

• H01M10/0525

  Rocking-chair batteries, i.e. batteries with lithium insertion or intercalation in both electrodes; Lithium-ion batteries · CPC title

• B32B37/06

  characterised by the heating method · CPC title

• B32B2323/04

  Polyethylene · CPC title

• B32B2457/10

  Batteries · CPC title