Structure and formation method of semiconductor device structure

Patent metadata

Field	Value
Publication number	US-9899271-B2
Application number	US-201615368322-A
Country	US
Kind code	B2
Filing date	Dec 2, 2016
Priority date	May 29, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element

First claim

What is claimed is:

1. A semiconductor device, comprising:
a fin structure over a semiconductor substrate;
a gate stack covering a portion of the fin structure, wherein the gate stack comprises a gate dielectric layer, a first layer over the gate dielectric layer, and a gate filling layer; and
an isolation element over the semiconductor substrate and adjacent to the gate stack, wherein the isolation element is in direct physical contact with the first layer and the gate dielectric layer and wherein the first layer separates the isolation element and the gate filling layer.

2. The semiconductor device of claim 1 , wherein the gate stack further comprises a barrier layer between the gate dielectric layer and the first layer.

3. The semiconductor device of claim 2 , wherein the gate stack further comprises a blocking layer between the first layer and the gate filling layer.

4. The semiconductor device of claim 1 , wherein the first layer extends along a sidewall of the isolation element.

5. The semiconductor device of claim 1 , wherein the first layer extends conformally over the fin structure and a sidewall of the isolation element.

6. The semiconductor device of claim 2 , wherein:
the isolation element comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, carbon-containing silicon oxide, a polymer, and combinations thereof;
the gate dielectric layer comprises a material selected from the group consisting of hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, and combinations thereof;
the barrier layer comprises a metal-containing material;
the first layer comprises a material selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide, aluminides, ruthenium, palladium, platinum, cobalt, nickel conductive metal oxides, and combinations thereof; and
the gate filling layer comprises a material selected from the group consisting of tungsten, aluminum, copper, cobalt, and combinations thereof.

7. The semiconductor device of claim 1 , wherein the gate stack resides within a trench in a dielectric layer and wherein the trench is successively filled by the gate dielectric layer, a barrier layer, the first layer, a blocking layer, and the gate filling layer.

8. The semiconductor device of claim 1 , wherein a first portion of the isolation element proximate the semiconductor substrate has a first width, and wherein a second portion of the isolation element distal the semiconductor substrate has a second width greater than the first width.

9. A semiconductor device, comprising:
a first fin structure and a second fin structure over a semiconductor substrate separated by a dielectric layer;
a first gate stack covering a portion of the first fin structure;
a second gate stack covering a portion of the second fin structure; and
an isolation element on the dielectric layer, between the first fin structure and the second fin structure, and adjacent to the first gate stack and the second gate stack, the isolation element electrically isolating the first gate stack and the second gate stack and being in contact with a sidewall of a first gate dielectric layer of the first gate stack and in contact with a sidewall of a second gate dielectric layer of the second gate stack, wherein the isolation element separates lower portions of the first and second gate stacks by a first distance and separates upper portions of the first and second gate stacks by a second distance less than the first distance.

10. The semiconductor device of claim 9 , wherein the first gate stack comprises a first work function layer that extends up a sidewall of the isolation element and the second gate stack comprises a second work function layer that extends up an opposite sidewall of the isolation element.

11. The semiconductor device of claim 9 , wherein the first gate stack comprises a first gate filling layer and a first work function layer, and wherein the first work function layer separates the isolation element from the first gate filling layer.

12. The semiconductor device of claim 11 , wherein the second gate stack comprises a second gate filling layer and a second work function layer, the second work function layer comprising a different material than the first work function layer, and wherein the second work function layer separates the isolation element from the second gate filling layer.

13. The semiconductor device of claim 12 , wherein the isolation element separates the first and second gate dielectric layers by the first distance and separates the first and second work function layers by the second distance.

14. The semiconductor device of claim 12 , further comprising a p-type transistor formed in the first fin structure and an n-type transistor formed in the second fin structure.

15. The semiconductor device of claim 12 , further comprising gate stack sidewall spacers on sidewalls of the first gate stack and on sidewall of the second gate stack.

16. The semiconductor device of claim 12 , wherein sidewalls of the isolation element form an angle relative to a bottommost surface of the isolation element of from about 10 degrees to about 85 degrees.

17. The semiconductor device of claim 11 , wherein the first gate stack further includes a first blocking layer between the first work function layer and the first gate filling layer.

18. A method for forming a semiconductor device structure, comprising:
forming a first fin structure and a second fin structure over a semiconductor substrate;
forming a dummy gate stack over the semiconductor substrate to partially cover the first fin structure and the second fin structure;
removing the dummy gate stack to form a trench over the semiconductor substrate;
forming a gate dielectric layer in the trench, the gate dielectric layer extending over the first fin structure and the second fin structure;
forming a metal containing barrier layer on the gate dielectric layer;
forming a recess in the gate dielectric layer and in the metal containing barrier layer;
forming an isolation element in the trench to fill the recess; and
forming a first gate electrode in the trench and in contact with a first sidewall of the isolation element and forming a second gate electrode in the trench and in contact with a second opposite sidewall of the isolation element, wherein the isolation element electrically isolates the first gate electrode and the second gate electrode.

19. The method of claim 18 , further comprising partially etching the isolation element to modify a sidewall profile of the isolation element.

20. The method of claim 18 , further comprising conformally depositing a work function layer on a sidewall of the isolation element.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che Cheng
• Chuang Jui Ping
• Lu Chen Hsiang
• Chen Wei Ting
• Liu Yu Cheng

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L29/24

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic