Low cost package warpage solution

Patent metadata

Field	Value
Publication number	US-9899238-B2
Application number	US-201414576166-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Dec 18, 2014
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

First claim

What is claimed is:

1. A method for forming a device package, comprising:
forming a reinforcement layer over a substrate, wherein one or more openings are formed through the reinforcement layer, wherein forming the reinforcement layer comprises:
placing a mold over the surface of the substrate;
injecting a molding material into the mold; and
removing the mold from the substrate;

placing a device die into one of the openings; and
bonding the device die to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate.

2. The method of claim 1 , wherein the mold comprises one or more recesses and a compliant liner.

3. The method of claim 1 , wherein the molding material is injected into the mold with an injection molding process.

4. The method of claim 3 , wherein the injection molding process is a vacuum assisted injection molding process.

5. The method of claim 1 , wherein the molding material is an epoxy.

6. The method of claim 5 , wherein the epoxy comprises reinforcement particles.

7. A method for forming a device package, comprising:
forming a reinforcement layer over a substrate, wherein one or more openings are formed through the reinforcement layer, wherein the reinforcement layer is steel, stainless steel, or aluminum, and wherein forming the reinforcement layer comprises:
applying an adhesive layer to a surface of the reinforcement layer; and
placing the reinforcement layer over the substrate, wherein the adhesive layer mechanically couples the reinforcement layer to the substrate;

placing a device die into one of the openings;
bonding the device die to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate.

8. The method of claim 1 , wherein the one or more solder bumps are formed on the device die prior to the device die being placed into the opening.

9. The method of claim 8 , wherein each of the one or more solder bumps are formed on separate metallic pillars that are electrically coupled to integrated circuitry of the device die.

10. The method of claim 1 , wherein a first gap between a first edge of the device die and a first sidewall of the opening is larger than a second gap between a second edge of the device die and a second sidewall of the opening.

11. A method for forming a device package, comprising:
forming a reinforcement layer over a substrate, wherein one or more openings are formed through the reinforcement layer;
placing a device die into one of the openings;

bonding the device die to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate; and
electrically and mechanically coupling a second die to a top surface of the device die, wherein a width of the second die is wider than a width of the opening, and wherein a portion of the second die is supported by the reinforcement layer.

12. The method of claim 11 , wherein the second die is a memory die that is electrically coupled to integrated circuitry of the device die by one or more through vias formed in the device die, one or more conductive traces formed over a surface of the device die, and one or more local memory interconnects formed over a surface of the device die.

13. The method of claim 1 , wherein a thickness of the substrate is less than approximately 100 μm.

Assignees

• Intel Corp

Inventors

• Karhade Omkar G
• Deshpande Nitin A
• Mallik Debendra
• Ziadeh Bassam M
• Tomita Yoshihiro

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title