Systems and methods for low voltage secure digital (SD) interfaces

Patent metadata

Field	Value
Publication number	US-9899105-B2
Application number	US-201314087047-A
Country	US
Kind code	B2
Filing date	Nov 22, 2013
Priority date	Nov 22, 2013
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Systems and methods for low voltage secure digital (SD) interfaces are disclosed. Embodiments of the present disclosure relate to systems and voltage for a lower voltage SD or SD Input/Output (SDIO) interface such as two integrated circuits. In particular, a SD or SDIO interface may be established between two SD compliant devices. While the SD compliant devices may otherwise comply with the SD standard, the voltage levels for signals passed between the SD compliant devices may be below 1.8 volts that the standard mandates. This reduced voltage is possible because the distances involved for interchip communication or the short distances involved for mobile terminal to peripheral connection are short enough that the reduced voltage is sufficient to still provide the desired signal strength at the receiver.

First claim

What is claimed is:

1. A method of interconnecting two secure digital (SD) compliant devices, comprising:
coupling a transmitting output of a first SD compliant device of two SD compliant devices to a receiving input of a second SD compliant device; and
operating according to an SD standard except that voltage levels at the transmitting output are less than 1.8 volts to achieve a logical high for signals.

2. The method of claim 1 , wherein the two SD compliant devices comprise secure digital input/output (SDIO) compliant devices.

3. The method of claim 2 , wherein the voltage levels comprise a peak of 1.2 volts or approximately 1.2 volts.

4. The method of claim 2 , wherein the voltage levels comprise a peak of approximately 1.5 volts.

5. The method of claim 2 , wherein coupling the transmitting output comprises coupling a differential output.

6. A method of interconnecting two secure digital (SD) compliant devices comprising:
coupling a transmitting output of a first SD compliant device of two SD compliant devices to a receiving input of a second SD compliant device; and
initially transmitting an otherwise SD compliant signal to the second SD compliant device at a first signal level below 1.8 volts representing a logical high;
determining if there is a response from the second SD compliant device; and
incrementing to a second signal level at or above 1.8 volts for transmission of the otherwise SD compliant signal.

7. The method of claim 6 wherein the two SD compliant devices comprise secure digital input/output (SDIO) compliant devices.

8. The method of claim 7 , wherein determining if there is a response comprises waiting a predetermined amount of time for the response.

9. The method of claim 7 , wherein initially transmitting the otherwise SD compliant signal to the second SD compliant device comprises transmitting a signal at a 1.2volt voltage level.

10. The method of claim 7 , wherein initially transmitting the otherwise SD compliant signal to the second SD compliant device comprises transmitting a signal at a 1.5volt voltage level.

11. The method of claim 7 , further comprising before incrementing to the second signal level above 1.8 volts incrementing to a third signal level above the first signal level but still below 1.8 volts.

12. The method of claim 11 , wherein the third signal level is 1.5 volts.

13. The method of claim 7 , wherein initially transmitting comprises transmitting a differential signal.

14. The method of claim 6 , further comprising determining an error indication for signals transmitted to and received from the second SD compliant device.

15. The method of claim 14 , wherein the error indication is a bit error rate.

16. The method of claim 14 , further comprising adjusting a voltage level for transmitted signals based on the error indication.

17. A host configured to operate using a secure digital (SD) standard with a remote device, the host comprising:
a transmitter configured to transmit a transmitted signal to a remote device; and
a receiver configured to receive a received signal from the remote device;
wherein the transmitted signal complies with an SD standard except that transmitted voltage levels for logical highs are less than 1.8 volts.

18. The host of claim 17 , wherein the host and the remote device are SD input/output (SDIO) compliant devices.

19. The host of claim 18 , wherein the received signal complies with the SD standard except that received voltage levels are less than 1.8 volts.

20. The host of claim 17 , wherein the transmitted voltage levels are selected from the group consisting of 1.2 and 1.5 volts.

21. A method of interconnecting two secure digital (SD) compliant devices comprising:
coupling a transmitting output of a first SD compliant device of two SD compliant devices to a receiving input of a second SD compliant device;
initially transmitting an otherwise SD compliant signal to the second SD compliant device at a first signal level;
receiving a reply from the second SD compliant device with a capability parameter relating to voltages for logical highs for signals; and
subsequently transmitting signals to the second SD compliant device at a voltage level based on the capability parameter, where the voltage level for the logical highs are below 1.8 volts.

22. The method of claim 21 , wherein the two SD compliant devices comprise SD input/output (SDIO) compliant devices.

23. A method of interconnecting two secure digital (SD) compliant devices comprising:
coupling a transmitting output of a first SD compliant device of two SD compliant devices to a receiving input of a second SD compliant device; and
initially transmitting an otherwise SD compliant signal to the second SD compliant device at a first signal level below 1.8 volts;
subsequently transmitting signals to the second SD compliant device;
determining an error indication for signals transmitted to and received from the second SD compliant device; and
adjusting a voltage level for transmitted signals based on the error indication.

Assignees

• Qualcomm Inc

Inventors

• Gerber Nir

Classifications

• G11C29/50004 Primary

  of threshold voltage · CPC title

• G06F13/4068 Primary

  Electrical coupling · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic