Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9899082-B2
Application number	US-201615261810-A
Country	US
Kind code	B2
Filing date	Sep 9, 2016
Priority date	Mar 3, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

According to one embodiment, a semiconductor memory device includes: a first memory cell including a first variable resistance element; a first buffer coupled to the first memory cell; a second memory cell including a second variable resistance element; and a second buffer coupled to the second memory cell. In data write, first data is stored in the first buffer and is transferred to the first memory cell, and second data is stored in the second buffer and is transferred to the second memory cell, and a start of the transferring the first data and the second data is based on a first data transfer signal.

First claim

What is claimed is:

1. A magnetic random access memory comprising:
a first memory cell including a first variable resistance element;
a first buffer coupled to the first memory cell;
a second memory cell including a second variable resistance element; and
a second buffer coupled to the second memory cell,
wherein in a write operation:
first data is stored in the first buffer when the memory receives a first write command and the first data,
second data is stored in the second buffer and is transferred to the second memory cell when the memory receives a second write command and the second data after the memory receives the first write command and the first data, and
the first data in the first buffer and the second data in the second buffer are transferred to the first memory cell and the second memory cell respectively when a first signal is generated a predetermined time after the memory receives the first write command, and
wherein:
the first variable resistance element and the second variable resistance element each include a first magnetic layer, a second magnetic layer, and a first non-magnetic layer provided between the first magnetic layer and the second magnetic layer,
the second magnetic layer has a greater inverted energy barrier in a magnetization direction than the first magnetic layer has,
when transferring the first data and the second data, a magnetization direction of the second magnetic layer is inverted for a first time, and
the first time is shorter than a second time which is a time after the first signal is generated and before the second signal is generated.

2. The memory of claim 1 , wherein in the write operation:
third data is stored in the second buffer when the memory receives a third write command and the third data after the first data and the second data are transferred to the first memory cell and the second memory cell respectively,
fourth data is stored in the first buffer when the memory receives a fourth write command and the fourth data after the memory receives the third write command and the third data, and
the third data in the second buffer and the fourth data in the first buffer are transferred to the second memory cell and the first memory cell respectively when a second signal is generated a predetermined time after the memory receives the third write command.

3. The memory of claim 1 , wherein the transferring the first data is executed in parallel, at least in part, with the transferring the second data.

4. The memory of claim 1 , wherein the first signal is generated based on a predetermined number of clock signals received from outside after the memory receives the first write command.

5. The memory of claim 1 , wherein the first signal is generated based on a predetermined number of write commands received from outside after the memory receives the first write command.

6. The memory of claim 2 ,
wherein the transferring the third data and the fourth data is started at a timing after a lapse of a time from a later one between a transfer completion of the first data and a transfer completion of the second data.

7. A magnetic random access memory comprising:
a first memory cell comprising a first variable resistance element;
a first buffer coupled to the first memory cell;
a second memory cell comprising a second variable resistance element; and
a second buffer coupled to the second memory cell,
wherein in a write operation:
first data is stored in the first buffer when the memory receives a first write command and the first data,
second data is stored in the first buffer when the memory receives a second write command and the second data after the memory receiving the first write command and the first data,
the second data in the first buffer is transferred to the first memory cell when a first signal is generated according to a timing at which the memory receives the first write command, and
the first data is not transferred to the first memory cell when the first signal is generated a predetermined time after the memory receives the first write command, and
wherein:
the first variable resistance element and the second variable resistance element each include a first magnetic layer, a second magnetic layer, and a first non-magnetic layer provided between the first magnetic layer and the second magnetic layer,
the second magnetic layer has a greater inverted energy barrier in a magnetization direction than the first magnetic layer has,
when transferring the first data and the second data, a magnetization direction of the second magnetic layer is inverted for a first time, and
the first time is shorter than a second time which is a time after the first signal is generated and before the second signal is generated.

8. The memory of claim 7 ,
wherein in the write operation:
third data is stored in the second buffer when the memory receives a third write command and the third data after the first data is transferred to the first memory cell,
fourth data is stored in the first buffer when the memory receives a fourth write command and the fourth data after the memory receives the third write command and the third data, and
the third data in the second buffer and the fourth data in the first buffer are transferred to the second memory cell and the first memory cell respectively when a second signal is generated a predetermined time after the memory receives the third write command.

9. The memory of claim 7 , wherein the first signal is generated based on a predetermined number of clock signals received from outside after the memory receives the first write command.

10. The memory of claim 7 , wherein the first signal is generated based on a predetermined number of write commands received from outside after the memory receives the first write command.

Assignees

• Toshiba Memory Corp

Inventors

• Katayama Akira

Classifications

• G11C13/0028

  Word-line or row circuits · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C2013/0085

  Write a page or sector of information simultaneously, e.g. a complete row or word line · CPC title