Metal line layout based on line shifting

Patent metadata

Field	Value
Publication number	US-9898572-B2
Application number	US-201615045466-A
Country	US
Kind code	B2
Filing date	Feb 17, 2016
Priority date	Feb 17, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A method of Back-End-Of-Line processing of a semiconductor device is provided including providing a layout for metal lines of a metallization layer of the semiconductor device, determining a semi-isolated metal line in the provided layout and shifting at least a portion of the determined semi-isolated metal line.

First claim

What is claimed:

1. A method, comprising:
providing a layout for metal lines of a metallization layer of a semiconductor device;
identifying a metal line in said layout as being a semi-isolated metal line;
determining a first portion of said identified semi-isolated metal line that is directly connected to a via formed in said metallization layer;
shifting at least a second portion of said identified semi-isolated metal line within said layout, wherein said shifting of at least said second portion of said identified semi-isolated metal line excludes said first portion of said identified semi-isolated metal line that is determined to be directly connected to said via; and
fabricating said semiconductor device based on said layout after said shifting.

2. The method of claim 1 , further comprising increasing at least one of a width and a length of said shifted at least a second portion of said identified semi-isolated metal line.

3. The method of claim 1 , wherein said identified semi-isolated metal line is neighbored to another metal line and wherein a distance of said at least a second portion of said identified semi-isolated metal line to said neighbored metal line is increased by said shifting.

4. The method of claim 3 , wherein said steps of identifying said metal line in said layout as being a semi-isolated metal line and shifting at least a second portion of said identified semi-isolated metal line are repeated for said neighbored metal line.

5. The method of claim 1 , wherein said identified semi-isolated metal line is shifted by a predetermined distance of one of ¼, ½ and 1 times a width of said identified semi-isolated metal line.

6. The method of claim 1 , wherein a metal line in said layout is identified as being a semi-isolated metal line when at least a portion of said metal line in said layout has a distance to a neighbored metal line of at least a predetermined value.

7. The method of claim 6 , wherein said predetermined value is one of 2, 3 or 4 times a width of said metal line in said layout.

8. The method of claim 1 , further comprising reading a pattern from a pattern catalog and wherein said shifting of said at least a second portion of said identified semi-isolated metal line is performed based on said read pattern.

9. The method of claim 1 , wherein said shifting of said at least a second portion of said identified semi-isolated metal line is performed based on a design rule.

10. A method, comprising
providing a first layout comprising a plurality of metal lines of a metallization layer of a semiconductor device;
identifying semi-isolated metal lines within said plurality of metal lines in said first layout;
shifting at least portions of said identified semi-isolated metal lines into available space in said first layout to generate a second layout such that said shifted portions of said identified semi-isolated metal lines are located further away from closest neighbored metal lines in said second layout than were said portions of said identified semi-isolated metal lines in said first layout prior to being shifted;
determining portions of said identified semi-isolated metal lines that are directly connected to vias formed in said metallization layer and wherein said shifting of at least portions of said identified semi-isolated metal lines into said available space excludes portions of said identified semi-isolated metal lines that are determined to be directly connected to said vias; and
fabricating said semiconductor device based on said layout after said shifting.

11. The method of claim 10 , further comprising defining shift windows based on said identified semi-isolated metal lines, said available space and said portions of said identified semi-isolated metal lines that are determined to be directly connected to said vias and wherein said shifting of said at least portions of said identified semi-isolated metal lines into said available space is performed by means of said defined shift windows.

12. The method of claim 10 , further comprising reading a pattern from a pattern catalog and wherein said shifting of said at least portions of said identified semi-isolated metal lines is performed based on said read pattern.

13. The method of claim 10 , further comprising increasing at least one of a width and a length of at least some of said shifted at least portions of said identified semi-isolated metal lines by means of an optical proximity correction technique.

14. The method of claim 10 , wherein metal lines of said metal lines of said first layout are determined to be semi-isolated metal lines when at least portions of said metal lines have distances to neighbored metal lines of at least a predetermined value selected from a range of 2 to 5 times a width of said metal lines.

15. The method of claim 10 , wherein said at least portions of said determined semi-isolated metal lines are shifted into available space of said first layout by a predetermined value selected from a range of 0.2 to 2 times a width of said metal lines.

16. The method of claim 10 , wherein said metallization layer is a second or higher metallization layer of an integrated circuit.

17. A method, comprising:
providing a layout for metal lines of a metallization layer of a semiconductor device;
identifying a metal line in said layout as being a semi-isolated metal line, wherein a metal line in said layout is identified as being a semi-isolated metal line when at least a portion of said metal line in said layout has a distance to a neighbored metal line of at least a predetermined value, and said predetermined value is one of 2, 3 or 4 times a width of said metal line in said layout;
shifting at least a portion of said identified semi-isolated metal line within said layout; and
fabricating said semiconductor device based on said layout after said shifting.

18. The method of claim 17 , further comprising increasing at least one of a width and a length of said shifted at least a portion of said identified semi-isolated metal line.

19. The method of claim 17 , wherein said identified semi-isolated metal line is neighbored to another metal line and wherein a distance of said at least a portion of said identified semi-isolated metal line to said neighbored metal line is increased by said shifting.

20. The method of claim 19 , wherein said steps of identifying said metal line in said layout as being a semi-isolated metal line and shifting at least a portion of said identified semi-isolated metal line are repeated for said neighbored metal line.

Assignees

• Globalfoundries Inc

Inventors

• Melde Thomas
• Lehr Matthias U
• Herrmann Thomas
• Hassmann Jens
• Meyer Moritz Andreas
• Kuncha Rakesh Kumar

Classifications

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F17/5077 Primary

  Physics · mapped topic

• H10D89/10 Primary

  Integrated device layouts · CPC title