Memory access processing method, memory chip, and system based on memory chip interconnection

Patent metadata

Field	Value
Publication number	US-9898421-B2
Application number	US-201514751368-A
Country	US
Kind code	B2
Filing date	Jun 26, 2015
Priority date	Dec 28, 2012
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A memory access processing method is based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present disclosure includes receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule, the memory access request to a next memory chip connected with the first memory chip, until the target memory chip corresponding to the memory access request is determined. Embodiments of the present disclosure are mainly used in a process of processing a memory access request.

First claim

What is claimed is:

1. A memory access processing method based on memory chip interconnection, comprising:
receiving, by a first memory chip, a memory access request that carries an indication of an urgency level;
sending, by the first memory chip according to a preconfigured routing rule and through a chip interconnect interface disposed on the first memory chip, the memory access request to a second memory chip connected with the chip interconnect interface when the first memory chip is not a target memory chip corresponding to the memory access request;
dividing, by the second memory chip, the memory access request into at least two secondary memory access requests;
sending, by the second memory chip, the at least two secondary memory access requests to a third memory chip and a fourth memory chip when the target memory chip is in a busy state, wherein the third memory chip and the fourth memory chip are connected to the target memory chip and are in an idle state; and
continuing to divide the at least two secondary memory access requests into additional secondary memory access requests until the target memory chip is in the idle state and receives one of the additional secondary memory access requests,
wherein the second memory chip is taken as the first memory chip for implementing the process, until the target memory chip corresponding to the memory access request is determined,
wherein the target memory chip comprises a cache of memory access requests, and
wherein the target memory chip processes the memory access requests according to urgency levels associated with the memory access requests.

2. The memory access processing method based on the memory chip interconnection according to claim 1 , wherein receiving, by the first memory chip, the memory access request comprises receiving, through a high-speed bus interface, the memory access request from a memory controller.

3. The memory access processing method based on the memory chip interconnection according to claim 1 , wherein receiving, by the first memory chip, the memory access request comprises receiving, through the chip interconnect interface, the memory access request from the second memory chip.

4. The memory access processing method based on the memory chip interconnection according to claim 1 , wherein after receiving, by the first memory chip, the memory access request, the method further comprises performing a memory access operation corresponding to the memory access request when the first memory chip is the target memory chip corresponding to the memory access request.

5. The memory access processing method based on the memory chip interconnection according to claim 4 , wherein before performing the memory access operation corresponding to the memory access request, the method further comprises:
caching, by the first memory chip, the memory access request received from the second memory chip as a cached memory access request when the first memory chip is in the busy state; and
reading, by the first memory chip, the cached memory access request when the first memory chip leaves the busy state.

6. The memory access processing method based on the memory chip interconnection according to claim 4 , wherein the memory access request comprises a data interaction instruction for instructing interaction between an interaction memory chip and the target memory chip, wherein the memory access request indicates memory service data to be interacted between the interaction memory chip and the target memory chip, and wherein performing the memory access operation corresponding to the memory access request comprises transmitting, according to the preconfigured routing rule, the memory service data indicated by the data interaction instruction between the interaction memory chip and the target memory chip.

7. The memory access processing method based on the memory chip interconnection according to claim 2 , wherein the memory access request from the memory controller comprises a primary memory access request received by the memory controller and/or one of the at least two secondary memory access requests that are divided from the primary memory access request.

8. A memory chip, comprising:
a receiver configured to receive a memory access request that carries an indication of an urgency level;
at least one chip interconnect interface coupled to the receiver and configured to be coupled to a second memory chip; and
a transmitter coupled to the at least one chip interconnect interface and configured to:
send, according to a preconfigured routing rule and through a chip interconnect interface, the memory access request to the second memory chip connected with the chip interconnect interface when the memory chip is not a target memory chip corresponding to the memory access request;
divide the memory access request into at least two secondary memory access requests;
send the at least two secondary memory access requests to a third memory chip and a fourth memory chip when the target memory chip is in a busy state, wherein the third memory chip and the fourth memory chip are connected to the target memory chip and are in an idle state; and
continue to divide the at least two secondary memory access requests into additional secondary memory access requests until the target memory chip is in the idle state and receives one of the additional secondary memory access requests,

wherein the target memory chip comprises a cache of memory access requests, and
wherein the target memory chip processes the memory access requests according to urgency levels associated with the memory access requests.

9. The memory chip according to claim 8 , wherein the receiver is further configured to receive, through a high-speed bus interface, the memory access request from a memory controller.

10. The memory chip according to claim 8 , wherein the receiver is further configured to receive, through the chip interconnect interface, the memory access request from the second memory chip.

11. The memory chip according to claim 8 , further comprising a processor configured to perform a memory access operation corresponding to the memory access request after the receiver receives the memory access request and when the memory chip is the target memory chip corresponding to the memory access request.

12. The memory chip according to claim 11 , wherein the cache is configured to cache the memory access request received from the other memory chip before the processor performs the memory access operation corresponding to the memory access request and when the memory chip is in the busy state, and wherein the processor is configured to read the cached memory access request when the memory chip leaves the busy state.

13. The memory chip according to claim 11 , wherein the memory access request comprises a data interaction instruction for instructing interaction between an interaction memory chip and the target memory chip, wherein the memory access request indicates memory service data to be interacted between the interaction memory chip and the target memory chip, and wherein the memory access operation corresponding to the memory access request comprises transmitting, according to the preconfigured routing rule, the memory service data between the interaction memory chip and the target memory chip.

14. The memory chip according to claim 9 , wherein the memory access request from the memory controller comprises a primary memory access request received by the memory controller and/or one of the at least two secondary memory access requests that are divided from the primary memory access request.

Assignees

• Huawei Tech Co Ltd

Inventors

• Huang Yongbing
• Chen Mingyu
• Ruan Yuan
• Chen Licheng

Classifications

• G06F2212/1052

  Security improvement · CPC title

• G11C7/1003

  Interface circuits for daisy chain or ring bus memory arrangements · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F13/1642 Primary

  with request queuing · CPC title

• G11C7/1075

  for multiport memories each having random access ports and serial ports, e.g. video RAM · CPC title