Method to share a coherent accelerator context inside the kernel

Patent metadata

Field	Value
Publication number	US-9898417-B2
Application number	US-201614986980-A
Country	US
Kind code	B2
Filing date	Jan 4, 2016
Priority date	Oct 16, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. According to one embodiment, a request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.

First claim

What is claimed is:

1. A method, comprising:
receiving a request from a first application to a coherent accelerator to perform an I/O operation within a kernel context, wherein the coherent accelerator shares virtual memory with a processor, wherein the request specifies a first effective address of a local effective address space distinct to the first application and wherein the first effective address specifies a location in the local effective address space of the kernel context and a first effective segment identifier;
remapping the first effective address to a second effective address in a global effective address space shared by the first application and at least a second application, wherein the second effective address specifies a location in the global effective address space of the kernel context and a second effective segment identifier;
determining, by a lookup using the second effective segment identifier on a page table and a shared segment table, a virtual address that maps to a virtual address space within the kernel context; and
translating the virtual address to a physical memory address.

2. The method of claim 1 , wherein the kernel context and segment table are shared with the first application and the second application.

3. The method of claim 1 , wherein the first and second addresses further specify a page number and a byte offset.

4. The method of claim 3 , wherein determining the virtual address comprises:
determining, via the shared segment table based on the second effective segment identifier, a virtual segment identifier; and
performing a lookup operation in the page table using the virtual segment identifier, page number, and the byte offset.

5. The method of claim 1 , further comprising:
inserting the I/O operation into a command queue.

6. The method of claim 5 , wherein the first application blocks other I/O operations until the I/O operation is completed.

7. The method of claim 1 , wherein the I/O operation is performed via the coherent accelerator.

Assignees

• IBM

Inventors

• Albot Andre L
• Aslot Vishal C
• Rogers Mark D
• Swanberg Randal C

Classifications

• G06F2212/1024

  Latency reduction · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F3/0611

  in relation to response time · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title