Hybrid main memory using a fine-grain level of remapping

Patent metadata

Field	Value
Publication number	US-9898410-B2
Application number	US-201414479676-A
Country	US
Kind code	B2
Filing date	Sep 8, 2014
Priority date	Sep 10, 2013
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Accessing a hybrid memory using a translation line is disclosed. The hybrid memory comprises a first portion. The translation line maps a first physical memory address to a first line in the first portion. Said mapping provides an indication that the first line is not immediately accessible in the first portion.

First claim

What is claimed is:

1. A hybrid memory system comprising:
a hybrid memory that includes a first portion; and
a hardware memory controller coupled with the hybrid memory, wherein the hardware memory controller is to:
access the hybrid memory with a first physical address, using a translation line, wherein the translation line is associated with a mapping of the first physical address to a first line in the first portion that is within a memory page, wherein the mapping provides an indication that the first line is not immediately accessible in the first portion, and the indication defines a reserved address in the first portion or a translation line tag.

2. The system of claim 1 , wherein the hybrid memory further includes a second portion, wherein the first portion has different characteristics compared to the second portion.

3. The system of claim 2 , wherein the first portion comprises volatile memory and the second portion comprises non-volatile memory.

4. The system of claim 2 , wherein the hardware memory controller is to remap by transferring line contents associated with the second portion to the first portion.

5. The system of claim 2 , wherein the hardware memory controller is to detect access to the second portion, prior to providing an access indication.

6. The system of claim 2 , wherein a second line associated with the second portion is unmapped and then an intervention action occurs when an associated processor attempts to access the second line.

7. The system of claim 1 , wherein the hardware memory controller is to, based at least in part on the indication, modify the translation line, wherein the modified translation line maps the first physical address to a first data line in the first portion that is readily accessible.

8. The system of claim 7 , wherein a separate data structure is used to determine the modification of the translation line to map the first physical address to the first data line in the first portion.

9. The system of claim 1 , wherein the hardware memory controller is to receive a remapping of the translation line from an auxiliary module.

10. The system of claim 1 , wherein the hardware memory controller is to prefetch other data lines.

11. The system of claim 1 , wherein the hardware memory controller is to remap lines associated with a virtual memory page.

12. The system of claim 11 , wherein the lines associated with the virtual memory page that have been remapped by the hardware memory controller permits an associated processor to continue after the translation line has mapped the first physical address to the first line in the first portion.

13. The system of claim 11 , wherein virtual address mapping is handled in software.

14. The system of claim 1 , wherein the hardware memory controller is to provide transactional update support.

15. The system of claim 2 , wherein the hardware memory controller is to support writing modified lines of memory to a log area in the second portion.

16. The system of claim 15 , wherein the modified lines of memory of writeback are recorded in the log area.

17. The system of claim 1 , wherein the hardware memory controller is to maintain an undo log area and a redo log area.

18. A method, comprising:
accessing a hybrid memory with a first physical memory address using a translation line, wherein the hybrid memory includes a first portion,
the translation line is associated with a mapping of the first physical memory
address to a first line in the first portion that is within a memory page,
the mapping provides an indication that the first line is not immediately accessible in the first portion,
and the indication defines a reserved address in the first portion or a translation line tag.

19. A method of supporting a hybrid main memory in hardware, comprising:
using a memory controller to remap at least in part by translating a plurality of physical memory addresses respectively associated with a plurality of current content locations;
associating the memory controller with the hybrid main memory, wherein the hybrid main memory includes a primary memory technology area and an alternative memory technology area;
associating the memory controller with a processor; and
on read of a physical address associated with an alternative data line that is currently stored in the alternative memory technology area, transferring the alternative data line to the processor and updating a mapping state to associate the physical address associated with the alternative data line with the primary memory technology area, wherein the alternative data line is a portion of a memory page.

20. The method of claim 19 , wherein a unit of transfer associated with transferring the alternative data line to the processor is a memory line.

21. The method of claim 19 , wherein one or more translation lines are used at least in part for remapping, and each of the one or more translations lines is to potentially remap multiple data lines.

22. The method of claim 19 , comprising updating another translation line to indicate availability of associated data lines in the primary memory technology area.

23. The method of claim 19 , comprising prefetching additional data lines referenced by another translation line into the primary memory technology area after a reference to the alternative data line.

24. The method of claim 19 , comprising providing line sharing between translation lines.

25. The method of claim 19 , comprising providing line granularity deduplication.

26. The method of claim 19 , comprising providing transactional update support.

27. The method of claim 19 , comprising, on write back of a data line from the processor, performing a write according to the update to the mapping state.

Assignees

• Intel Corp

Inventors

• Cheriton David R

Classifications

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title