Computing performance and power management with firmware performance data structure

Patent metadata

Field	Value
Publication number	US-9898306-B2
Application number	US-201715396726-A
Country	US
Kind code	B2
Filing date	Jan 2, 2017
Priority date	Nov 22, 2011
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.

First claim

What is claimed is:

1. A computing platform comprising:
a memory to store firmware boot program; and
a processor to execute the firmware boot program,
wherein the memory is to further store instructions to maintain a S 3 performance table that is to track one or both of:
first one or more parameters associated with S 3 resume performance, or
second one or more parameters associated with S 3 suspend performance.

2. The computing platform of claim 1 , wherein:
the S 3 performance table is to maintain a count of a number of S 3 resume cycles since a last full boot sequence of the processor.

3. The computing platform of claim 1 , wherein:
the S 3 performance table is to maintain a time at which the firmware boot program is to transition control to an operating system (OS) waking vector during a S 3 resume cycle.

4. The computing platform of claim 1 , wherein:
the S 3 performance table is to maintain an average timer value of all S 3 resume cycles logged since a last full boot sequence of the processor.

5. The computing platform of claim 1 , wherein:
the S 3 performance table is to maintain a timer value recorded at a final firmware write to trigger a hardware entry to the S 3 system sleep state.

6. The computing platform of claim 1 , wherein:
the memory is to further store instructions to maintain a firmware performance data table (FPDT) structure.

7. The computing platform of claim 6 , wherein:
the FPDT structure is to include a S 3 performance table pointer record containing a pointer to the S 3 performance table.

8. The computing platform of claim 6 , wherein:
the FPDT structure is to include a firmware basic boot performance pointer record containing a pointer to a firmware basic boot performance table.

9. A computing platform, comprising:
a memory to store firmware boot program; and
a processor to execute the firmware boot program,
wherein the memory is to further store instructions to maintain a firmware performance data table (FPDT) structure, and
wherein the FPDT structure is to include a record containing a pointer to a firmware basic boot performance table.

10. The computing platform of claim 9 , wherein:
the firmware basic boot performance table is to record a timer value logged at a beginning of a firmware image execution.

11. The computing platform of claim 9 , wherein:
the firmware basic boot performance table is to record a timer value logged immediate prior to loading an operating system (OS) boot loader into the memory.

12. The computing platform of claim 9 , wherein:
the firmware basic boot performance table is to record a timer value logged immediate prior to launching a currently loaded (OS) boot loader image.

13. The computing platform of claim 9 , wherein:
the firmware basic boot performance table is to record a timer value logged at a point where a (OS) loader calls a ExitBootServices function for Unified Extensible Firmware Interface (UEFI) compatible firmware.

14. The computing platform of claim 9 , wherein:
the firmware basic boot performance table is to record a timer value logged at a point immediate prior to a (OS) loader gaining control back from a ExitBootServices function for Unified Extensible Firmware Interface (UEFI) compatible firmware.

15. The computing platform of claim 9 , wherein:
the FPDT structure is to include a record containing a pointer to a S 3 performance table that is to track one or more parameters associated with one or both of: first one or more parameters associated with S 3 resume performance, or second one or more parameters associated with S 3 suspend performance.

16. The computing platform of claim 9 , wherein:
the FPDT structure is an Advanced Configuration and Power Interface (ACPI) data structure.

17. An apparatus, comprising:
a computer platform having firmware including Advanced Configuration and Power Interface (ACPI) components to build a S 3 performance table for an ACPI interface,
wherein the S 3 performance table is to track one or both of: first one or more parameters associated with S 3 resume performance, or second one or more parameters associated with S 3 suspend performance.

18. The apparatus of claim 17 , wherein:
the S 3 performance table is to track another one or more parameters associated with the boot program while the apparatus is to enter the system sleep state.

19. The apparatus of claim 17 , wherein:
the ACPI components is to build a firmware performance data table (FPDT) structure that is to include a record containing a pointer to the S 3 performance table.

20. The apparatus of claim 19 , wherein:
the FPDT structure that is to include a record containing a pointer to a firmware basic boot performance table that is to track one or more firmware boot parameters during a boot process.

21. The apparatus of claim 17 , further comprising:
a memory to store the S 3 performance table; and
a processor coupled to the memory.

Assignees

• Intel Corp

Inventors

• Rothman Michael
• Gough Robert
• Doran Mark

Classifications

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F11/3672

  Test management · CPC title

• G06F15/7871

  Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS · CPC title

• G06F11/3409

  for performance assessment · CPC title

• G06F11/3447

  Performance evaluation by modeling · CPC title