Memory access processing method, apparatus, and system

Patent metadata

Field	Value
Publication number	US-9898206-B2
Application number	US-201615017081-A
Country	US
Kind code	B2
Filing date	Feb 5, 2016
Priority date	Aug 6, 2013
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A memory access processing method and apparatus, and a system. The method includes receiving a memory access request sent by a processor, combining multiple memory access requests received within a preset time period to form a new memory access request, where the new memory access request includes a code bit vector corresponding to memory addresses. A first code bit identifier is configured for the code bits that are in the code bit vector and corresponding to the memory addresses accessed by the multiple memory access requests. The method further includes sending the new memory access request to a memory controller, so that the memory controller executes a memory access operation on a memory address corresponding to the first code bit identifier. The method effectively improves memory bandwidth utilization.

First claim

What is claimed is:

1. A memory access request processing method implemented by a memory access processing apparatus, the method comprising:
receiving a first memory access request and a second memory access request, wherein a length of a first memory address of the first memory access request and a second memory address of the second memory access request is A bits;
combining the first memory access request and the second memory access request to form a third memory access request, wherein the third memory access request comprises a code bit vector comprising:
N code bits comprising a first code bit corresponding to the first memory address and indicating the first memory access request and a second code bit corresponding to the second memory address and indicating the second memory access request,
a memory access granularity of L bytes,
a base address of the first memory address and the second memory address and comprising (A−log 2 (N*L)) bits, and
a memory access request type; and

sending the third memory access request to a memory controller.

2. The method according to claim 1 , wherein the combining comprises:
collecting, to a row of an address index table, the first memory access request and the second memory access request, wherein the row comprises the memory access request type, the base address, the memory access granularity, and the code bit vector; and
extracting the memory access request type, the base address, the memory access granularity, and the code bit vector from the row to form the third memory access request.

3. The method according to claim 1 , wherein when the memory access request type is a read memory operation, after the sending, the method further comprises:
writing data returned after the memory controller executes the read memory operation according to the third memory access request to a cache integrated in the processor; and
updating the first code bit identifier.

4. The method according to claim 1 , wherein when the memory access request type is a write memory operation, after sending the third memory access request to a memory controller, the method further comprises:
sending data corresponding to the write memory operation and read from a cache of the processor to the memory controller; and
updating the first code bit identifier.

5. The method according to claim 1 , further comprising:
determining, by a processing logic, that the first memory address is in a programmable on-chip memory (POM) address space;
sending, by the processing logic, the first memory access request to an address selector; and
sending, by the address selector, the first memory access request to the POM.

6. A memory access processing apparatus comprising:
a processor; and
a memory coupled to the processor and comprising a plurality of instructions, that when executed by the processor, cause the processor to:
receive a first memory access request and a second memory access request, wherein a length of a first memory address of the first memory access request and a second memory address of the second memory access request is A bits;
combine the first memory access request and the second memory access request to form a third memory, access request, wherein the third memory access request comprises a code bit vector comprising:
N code bits comprising a first code bit corresponding to the first memory address and indicating the first memory access request and a second code bit corresponding to the second memory address and indicating the second memory access request,
a memory access granularity of L bytes,
a base address of the first memory address and the second memory address and comprising (A−log 2 (N*L)) bits, and
a memory access request type; and

send the third memory access request to a memory controller.

7. The apparatus according to claim 6 , wherein the instructions further cause the processor to:
collect, to a row of an address index table, the first memory access request and the second memory access request, wherein the row comprises the memory access request type, the base address, the memory access granularity, and the code bit vector; and
extract the memory access request type, the base address, the memory access granularity, and the code bit vector from the row to form the third memory access request.

8. The apparatus according to claim 6 , wherein when the memory access request type is a read memory operation, the instructions further cause the processor of the apparatus to:
write data returned after the memory controller executes the read memory operation according to the third memory access request to a cache integrated in the processor; and
update the first code bit identifier.

9. The apparatus according to claim 6 , wherein when the memory access request type is a write memory operation, the instructions further cause the processor of the apparatus to:
send data corresponding to the write memory operation and read from a cache of the processor to the memory controller; and
update the first code bit identifier.

10. A memory access system comprising:
a processor;
an off-chip memory coupled to the processor;
a memory controller; and
a memory access processing apparatus coupled to the processor and the memory controller and configured to:
receive a first memory access request and a second memory access request that are sent by the processor, wherein a length of a first memory address of the first memory access request and a second memory address of the second memory access request is A bits:
combine the first memory access request and the second memory access request to form a third memory access request, wherein the third memory access request comprises a code bit vector comprising:
N code bits comprising a first code bit corresponding to the first memory access request and a second code bit corresponding to the second memory access request,
a memory access granularity of L bytes,
a base address of the first memory address and the second memory address and comprising (A−log 2 (N*L)) bits, and
a memory access request type; and

send the third memory access request to the memory controller,

wherein the memory controller is configured to:
receive the third memory access request;
obtain, by parsing the third memory access request, the first memory address and the second memory address; and
execute a memory access operation on the first memory address and the second memory address.

11. The system according to claim 10 , wherein the memory access processing apparatus is further configured to:
collect, to a row of an address index table, the first memory access request and the second memory access request, wherein the row comprises the memory access request type, the base address, the memory access granularity, and the code bit vector; and
extract the memory access request type, the base address, the memory access granularity, and the code bit vector from the row to form the third memory access request.

12. The system according to claim 10 , wherein when the memory access request type is a read memory operation, the memory controller is further configured to:
parse the third memory access request to obtain the first memory address;
read data stored in the first memory address, and
return the data to the memory access processing apparatus, and
wherein the memory access processing apparatus is further configured to:
write the data to a cache integrated in the processor; and
update the first code bit identifier.

13. The system according to claim 10 , wherein when the memory access request type of the third memory access request is a write memory operation, th

Assignees

• Huawei Tech Co Ltd

Inventors

• Fan Dongrui
• Song Fenglong
• Wang Da
• Ye Xiaochun

Classifications

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F9/3824 Primary

  Operand accessing · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title