Dynamic demodulation waveform adjustment for tonal noise mitigation
US-10042486-B1 · Aug 7, 2018 · US
US9898193B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9898193-B2 |
| Application number | US-201314372482-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 21, 2013 |
| Priority date | Jan 23, 2012 |
| Publication date | Feb 20, 2018 |
| Grant date | Feb 20, 2018 |
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An application-specific integrated circuit comprises: analog inputs having analog-digital converters; at least one digital signal processor, which has input registers and output registers. The analog-digital converters sample and digitize input signals S i with sampling frequencies f Si and forward the digitized signals SD i with output frequencies f SD-out-i to the input registers of the digital signal processor. The digital signal processor processes the digitized signals SD i to m processed signals SP j and forwards such to the output registers of the digital signal processor. The digital signal processor has a clock frequency, wherein, furthermore, the signals of the output registers can be output, respectively read-out, with an output frequency. One or more of the frequencies is, respectively, variable, wherein especially one or more of the frequencies, respectively, variable independently of the others of the frequencies.
Opening claim text (preview).
The invention claimed is: 1. An electronic circuit, especially an integrated circuit, especially an application-specific integrated circuit, comprising: n analog inputs having analog-digital converters, wherein n>=1; and at least one digital processor, especially a digital signal processor, which has input registers and output registers, wherein: said one or more analog-digital converters sample and digitize input signals S i (which depend on present values of measured variables) with sampling frequencies f Si and forward said digitized signals SD i with output frequencies f SD-out-i to said input registers of the digital signal processor; said digital signal processor processes the digitized signals SD i to m processed signals SP j and forwards such to said output registers of said digital signal processor, said digital signal processor has a clock frequency f DSP ; m>=1, and j=1, . . . , m; furthermore, the signals SP j of said output registers can be output, respectively read-out, with an output frequency f SP-out-j ; one or more of the frequencies f SD-out-i , f DSP , f SP-out-j are, variable independently of the others of said frequencies; said one or more frequencies depends, at least on at least one of said digitized measurement signals SD i or on a variable dependent thereon; and said one or more frequencies f DSP , f SP-out-j depends, on the standard deviation of said at least one digitized measurement signal SD i or a variable dependent thereon. 2. The application-specific integrated circuit as claimed in claim 1 , wherein: said one or more frequencies f SD-out-i , f DSP , f SP-out-j depends, on the time derivative and/or on another function dependent on the time behavior of said at least one digitized measurement signal SD i .
by lowering clock frequency · CPC title
by measuring pressure or differential pressure · CPC title
Digital input using the sampling of an analogue quantity at regular intervals of time {, input from a/d converter or output to d/a converter} · CPC title
Synchronisation of the sampling frequency or phase to the input frequency or phase · CPC title
by measurement of pressure · CPC title
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