Method and apparatus to configure thermal design power in a microprocessor

Patent metadata

Field	Value
Publication number	US-9898066-B2
Application number	US-201514645330-A
Country	US
Kind code	B2
Filing date	Mar 11, 2015
Priority date	Dec 21, 2010
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A technique to change a thermal design power (TDP) value. In one embodiment, one or more environmental or user-driven changes may cause a processor's TDP value to be changed. Furthermore, in some embodiments a change in TDP may alter a turbo mode target frequency.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores;
an integrated memory controller to communicatively couple the cores to a system memory;
first circuitry to set a thermal design power (TDP) setting in a Basic Input/Output System (BIOS) based on a user selection in a user interface for the processor and to change a configurable power limit value for the processor based on the TDP setting, wherein the configurable power limit value is to limit a power consumption of the processor,
second circuitry to read the configurable power limit value and write, in a register of a first core, power state information associated with the configurable power limit value, the power state information including a maximum power state for the first core and indicating one of a plurality of power states in which the first core is to currently operate,
wherein the plurality of power states includes at least one low power state and at least one turbo mode state;
a level one cache integral to each one of the plurality of cores;
a first shared cache shared by two or more of the plurality of cores; and
an inter-processor interconnect to communicatively couple the plurality of cores to cores of one or more other processors.

2. The processor of claim 1 , wherein the power state information is associated with one of a plurality of Advanced Configuration and Power Interface (ACPI) power states.

3. The processor of claim 1 , wherein each of the plurality of power states maps to a distinct frequency to operate one core.

4. The processor of claim 3 , wherein mapped frequencies comprise a plurality of frequencies that have an integer number of an offset frequency from a base frequency.

Assignees

• Intel Corp

Inventors

• Distefano Eric
• Therien Guy M
• Srinivasan Vasudevan
• Rahal Arabi Tawfik
• Ramani Venkatesh
• Wells Ryan D
• Gunther Stephen H
• Shrall Jeremy
• Hermerding Ii Hames

Classifications

• G06F1/206 Primary

  comprising thermal management · CPC title

• G06F1/3234 Primary

  Power saving characterised by the action undertaken · CPC title

• Y02B60/1275

  Cross-Sectional Technologies · mapped topic

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/324

  by lowering clock frequency · CPC title