Low voltage, highly accurate current mirror

Patent metadata

Field	Value
Publication number	US-9898028-B2
Application number	US-201514755435-A
Country	US
Kind code	B2
Filing date	Jun 30, 2015
Priority date	Nov 20, 2014
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Certain aspects of the present disclosure generally relate to a low voltage, accurate current mirror, which may be used for distributed sensing of a remote current in an integrated circuit (IC). One example current mirror typically includes a first pair of transistors, a second pair of transistors in cascode with the first pair of transistors, a switching network coupled to the second pair of transistors, and a third pair of transistors coupled to the switching network. An input node between the first and second pairs of transistors may be configured to receive an input current for the current mirror, and an output node at the first pair of transistors may be configured to sink an output current for the current mirror, proportional to the input current. This current mirror architecture offers a hybrid low-voltage/high-voltage solution, tolerates low input voltages, provides high output impedance, and offers low area and power consumption.

First claim

What is claimed is:

1. A current mirror comprising:
a first pair of transistors;
a second pair of transistors in cascode with the first pair of transistors;
a switching network coupled to the second pair of transistors;
a third pair of transistors coupled to the switching network, wherein an input node between the first and second pairs of transistors is configured to receive an input current for the current mirror and wherein a terminal of a transistor of the first pair of transistors is configured to sink an output current for the current mirror that is proportional to the input current; and
a current source configured to supply a bias current to another transistor in the first pair of transistors.

2. The current mirror of claim 1 , wherein the switching network is configured to periodically interchange connections between the second pair of transistors and the third pair of transistors.

3. The current mirror of claim 1 , wherein the switching network comprises a dynamic element matching (DEM) circuit.

4. The current mirror of claim 1 , wherein the bias current is negligible compared to the input current.

5. The current mirror of claim 1 , further comprising a source follower coupled to the current source and to the other transistor in the first pair of transistors.

6. The current mirror of claim 5 , wherein:
the source follower comprises a first transistor and a second transistor in cascode with the first transistor;
a gate of the first transistor is coupled to the current source and to a drain of the other transistor in the first pair of transistors; and
a source of the first transistor is coupled to at least one of a drain of the second transistor or a gate of the second transistor.

7. The current mirror of claim 6 , wherein the source follower further comprises at least one of:
a first capacitor connected between the gate of the first transistor and the source of the first transistor; or
a second capacitor connected between the gate of the first transistor and a source of the other transistor in the first pair of transistors, wherein the source of the other transistor in the first pair of transistors is coupled to the input node.

8. The current mirror of claim 6 , wherein the gate of the second transistor is coupled to gates of the third pair of transistors.

9. The current mirror of claim 1 , wherein a source of the other transistor in the first pair of transistors is coupled to the input node and wherein a drain of the transistor in the first pair of transistors is coupled to an output node of the current mirror.

10. The current mirror of claim 1 , wherein the current source is coupled to a first power supply node and wherein the third pair of transistors is coupled to a second power supply node having a lower voltage than the first power supply node.

11. The current mirror of claim 1 , wherein a ratio between the input current of the current mirror and the output current of the current mirror is 15:1.

12. The current mirror of claim 1 , wherein a transistor in the second pair of transistors separates the input node from the switching network.

13. The current mirror of claim 1 , wherein the input node, the second pair of transistors, the switching network, and the third pair of transistors operate in a low voltage domain and wherein an output node of the current mirror and the first pair of transistors operate in a high voltage domain.

14. The current mirror of claim 13 , wherein the second pair of transistors is configured to reduce charge sharing between the low voltage domain and the high voltage domain.

15. The apparatus of claim 1 , wherein a drain of the other transistor in the first pair of transistors is coupled to the current source and to gates of the third pair of transistors.

16. A current mirror comprising:
a first pair of transistors comprising a transistor and another transistor;
a second pair of transistors in cascode with the first pair of transistors;
a switching network coupled to the second pair of transistors; and
a third pair of transistors coupled to the switching network, wherein:
an input node between the first and second pairs of transistors is configured to receive an input current for the current mirror;
a terminal of the transistor of the first pair of transistors is configured to sink an output current for the current mirror that is proportional to the input current;
the second pair of transistors comprises a first transistor and a second transistor;
a gate of the first transistor is coupled to a gate of the second transistor;
a source of the other transistor is coupled to a drain of the first transistor; and
a source of the transistor is coupled to a drain of the second transistor.

17. The current mirror of claim 16 , wherein a gate of the transistor is coupled to a gate of the other transistor.

18. The current mirror of claim 16 , wherein:
the third pair of transistors comprises a third transistor and a fourth transistor;
a gate of the third transistor is coupled to a gate of the fourth transistor; and
a first size ratio between the first transistor and the second transistor equals a second size ratio between the third transistor and the fourth transistor.

19. The current mirror of claim 18 , wherein a third size ratio between the transistor and the other transistor is different from the first size ratio and the second size ratio.

20. The current mirror of claim 19 , wherein:
the third size ratio is based on a ratio between a bias current of the current mirror and the output current of the current mirror;
a drain of the other transistor is configured to receive the bias current; and
a drain of the transistor is configured to sink the output current.

21. The current mirror of claim 20 , wherein the bias current is less than the input current and wherein a source of the other transistor and a drain of the first transistor are coupled to the input node.

22. The current mirror of claim 18 , wherein:
in a first configuration of the switching network, a source of the first transistor is coupled to a drain of the third transistor and a source of the second transistor is coupled to a drain of the fourth transistor; and
in a second configuration of the switching network, the source of the first transistor is coupled to the drain of the fourth transistor and the source of the second transistor is coupled to the drain of the third transistor.

23. The current mirror of claim 16 , wherein the other transistor and the first transistor are in an input and bias currents branch of the current mirror and wherein the transistor and the second transistor are in an output current branch of the current mirror.

24. The current mirror of claim 16 , wherein the second transistor has a smaller size than the first transistor.

25. A current mirror comprising:
a first pair of transistors comprising a transistor and another transistor;
a second pair of transistors in cascode with the first pair of transistors;
a switching network coupled to the second pair of transistors; and
a third pair of transistors coupled to the switching network, wherein:
an input node between the first and second pairs of transistors is configured to receive an input current for the current mirror;
a terminal of the transistor of the first pair of transistors is configured to sink an output current for the current mirror that is proportional to the input current; and
the transistor ha

Assignees

• Qualcomm Inc

Inventors

• Roham Masoud
• Dai Liang

Classifications

• G01R19/0092

  Measuring current only · CPC title

• G05F3/262 Primary

  using field-effect transistors only · CPC title

• H03F3/505

  with field-effect devices · CPC title

• H03F3/347

  in integrated circuits · CPC title

• H03F2200/474

  A current mirror being used as sensor · CPC title