Array substrate, display panel and display apparatus having recesses on data lines or gate lines

Patent metadata

Field	Value
Publication number	US-9897863-B2
Application number	US-201514769303-A
Country	US
Kind code	B2
Filing date	Apr 10, 2015
Priority date	Oct 27, 2014
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

An array substrate, a display panel and a display apparatus are disclosed. The array substrate includes a plurality of gate lines ( 10; 50 ) and a plurality of data lines ( 30; 51 ), and pixel units arranged in an array. Each of the pixel units includes one pixel electrode ( 41; 42 ) and one thin film transistor, the data line ( 30; 51 ) serve as a source electrode ( 31; 311 ) of the thin film transistor, the gate line ( 10; 50 ) serve as a gate electrode ( 11 ) of the thin film transistor, and a drain electrode ( 32; 321; 322 ) of the thin film transistor is electrically connected to the pixel electrode ( 41; 42 ), at least one of the gate lines ( 10; 50 ) and the data lines ( 30; 51 ) has a recess ( 363; 364 ) provided thereon aligned with a spacer for fixing. With the recess ( 363; 364 ), the post spacer is prevented from moving to affect the display region when the substrate is bent and deformed under an external pressure.

First claim

What is claimed is:

1. An array substrate, comprising: a plurality of gate lines and a plurality of data lines, pixel units that are provided on the array substrate and arranged in an array, wherein,
each of the pixel units includes a pixel electrode and a thin film transistor, one of the data lines serves as a source electrode of the thin film transistor, one of the gate lines serves as a gate electrode of the thin film transistor, a drain electrode of the thin film transistor is electrically connected to the pixel electrode, and
at least two recesses each configured for fixing a spacer and disposed opposite to the spacer are provided on one of the data lines or one of the gate lines, and the at least two recesses have different kinds of shapes in a plane parallel to the array substrate.

2. The array substrate according to claim 1 , wherein the at least two recesses include a circular recess and/or a rectangular recess.

3. The array substrate according to claim 1 , wherein the at least two recesses include a polygonal recess.

4. The array substrate according to claim 1 , wherein one of the two recesses is provided with a conductive layer therein, which is formed in the same layer as the pixel electrode and is spaced apart from the pixel electrode.

5. The array substrate according to claim 1 , wherein the drain electrode is electrically connected to the pixel electrode through a via hole, or the pixel electrode is directly taped to the drain electrode.

6. The array substrate according to claim 5 , wherein the drain electrode is electrically connected to the pixel electrode through the via hole; the at least two recesses and the via hole are in a same layer.

7. A display panel, comprising the array substrate according to claim 1 .

8. A display apparatus, comprising the display panel according to claim 7 .

9. The display apparatus according to claim 8 , wherein, the display apparatus is a liquid crystal display apparatus.

10. The array substrate according to claim 1 , wherein the at least two recesses have different depths.

11. An array substrate, comprising: a plurality of gate lines and a plurality of data lines, pixel units that are provided on the array substrate and arranged in an array, wherein,
each of the pixel units includes a pixel electrode and a thin film transistor, one of the data lines serves as a source electrode of the thin film transistor, one of the gate lines serves as a gate electrode of the thin film transistor, a drain electrode of the thin film transistor is electrically connected to the pixel electrode, and
at least two recesses each configured for fixing a spacer and disposed opposite to the spacer are provided on one of the data lines or one of the gate lines, the at least two recesses have different depths, and at least one of the at least two recesses has an insulating surface, directly on which the spacer is to be disposed.

12. The array substrate according to claim 11 , wherein the at least two recesses include a circular recess and/or a rectangular recess.

13. The array substrate according to claim 11 , wherein the at least two recesses include a polygonal recess.

14. The array substrate according to claim 11 , wherein one of the at least two recesses is provided with a conductive layer therein, which is formed in the same layer as the pixel electrode and is spaced apart from the pixel electrode.

15. The array substrate according to claim 11 , wherein the drain electrode is electrically connected to the pixel electrode through a via hole, or the pixel electrode is directly taped to the drain electrode.

16. A display panel, comprising the array substrate according to claim 11 .

17. A display apparatus, comprising the display panel according to claim 16 .

Assignees

• Boe Technology Group Co Ltd

Inventors

• Li Wenbo
• Li Pan
• Xian Jianbo
• Cheng Hongfei

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10P14/3454

  Amorphous · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title