Semiconductor device and recording device

Patent metadata

Field	Value
Publication number	US-9895879-B2
Application number	US-201615383513-A
Country	US
Kind code	B2
Filing date	Dec 19, 2016
Priority date	Dec 21, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A semiconductor device includes, an anti-fuse element, a transistor connected via the anti-fuse element to a power source terminal which may apply a voltage to the anti-fuse element, an ESD protection element connected to the power source terminal via a node, and a first resistive element disposed in an electric path between the node and the anti-fuse element, wherein resistance of the first resistive element increases with an increase of a voltage applied to the first resistive element.

First claim

What is claimed is:

1. A semiconductor device comprising:
an anti-fuse element;
a transistor connected, via the anti-fuse element, to a power source terminal which is for applying a voltage to the anti-fuse element;
an electro-static discharge (ESD) protection element connected to the power source terminal via a node; and
a first resistive element disposed in an electric path between the node and the anti-fuse element,
wherein a resistance value of the first resistive element increases with an increase of a voltage applied to the first resistive element.

2. The semiconductor device according to claim 1 , wherein the anti-fuse element has a metal-oxide semiconductor (MOS) structure and is configured so that information is written therein through a dielectric breakdown of a gate oxide film of the MOS structure.

3. The semiconductor device according to claim 1 , wherein the transistor is a MOS transistor.

4. The semiconductor device according to claim 1 , further comprising:
a MOS transistor; and
a drive unit configured to drive the transistor.

5. The semiconductor device according to claim 1 , wherein, when the voltage applied to the first resistive element increases, the resistance value of the first resistive element monotonically increases and a rate of increase in the resistance value also monotonically increases.

6. The semiconductor device according to claim 1 , further comprising:
a second resistive element connected in parallel to the anti-fuse element,
wherein, when a voltage higher than a voltage applied to the power source terminal at the time of information writing in the anti-fuse element is applied, the rate of increase in the resistance value of the first resistive element is larger than a rate of increase in a resistance value of the second resistive element.

7. The semiconductor device according to claim 6 , wherein the first and the second resistive elements are diffusion resistors.

8. The semiconductor device according to claim 7 , wherein a width of the second resistive element is larger than a width of the first resistive element.

9. The semiconductor device according to claim 7 , wherein, in each of the first and the second resistive elements, a region to be a depletion layer region in a diffusion region where the diffusion resistor is formed is changed by an applied voltage, and a width of a region that substantially functions as a resistor decreases when a high voltage is applied.

10. The semiconductor device according to claim 1 , wherein the ESD protection element includes a MOS transistor of which a gate, a source, and a back gate are connected to a ground, and a drain is connected to the node between the power source terminal and the first resistive element.

11. A recording device comprising:
a recording head unit having discharge nozzles and a recording head substrate; and
an ink tank attached to the recording head unit,
wherein the recording head substrate comprises:
discharge elements each of which corresponds to a different one of the discharge nozzles;
a control circuit electrically connected to the discharge elements; and
the semiconductor device electrically connected to the control circuit, wherein the semiconductor device comprises:
an anti-fuse element;
a transistor connected, via the anti-fuse element, to a power source terminal which is for applying a voltage to the anti-fuse element;
an electro-static discharge (ESD) protection element connected to the power source terminal via a node; and
a first resistive element disposed in an electric path between the node and the anti-fuse element,
wherein a resistance value of the first resistive element increases with an increase of a voltage applied to the first resistive element.

12. A semiconductor device comprising:
an anti-fuse element;
a transistor of which either one of a source and a drain is connected to one terminal of the anti-fuse element and the other one of the source and the drain is supplied with a first potential;
a first resistive element of which one terminal is connected to the other terminal of the anti-fuse element and the other terminal is connected to a power source terminal supplied with a second potential different from the first potential; and
an ESD protection element connected to an electric path between the power source terminal and the other terminal of the first resistive element,
wherein the first resistive element is a diffusion resistor.

13. The semiconductor device according to claim 12 , wherein the anti-fuse element has a MOS structure and is configured so that information is written therein through a dielectric breakdown of a gate oxide film of the MOS structure.

14. The semiconductor device according to claim 12 , wherein the transistor is a MOS transistor.

15. The semiconductor device according to claim 12 , further comprising:
a MOS transistor; and
a drive unit configured to drive the transistor.

16. The semiconductor device according to claim 12 , wherein, when the voltage applied to the first resistive element increases, the resistance value of the first resistive element monotonically increases and a rate of increase in the resistance value also monotonically increases.

17. The semiconductor device according to claim 12 , further comprising:
a second resistive element connected in parallel to the anti-fuse element,
wherein, when a voltage higher than a voltage applied to the power source terminal at the time of information writing in the anti-fuse element is applied, the rate of increase in the resistance value of the first resistive element is larger than a rate of increase in a resistance value of the second resistive element.

18. The semiconductor device according to claim 12 , wherein a width of the second resistive element is larger than a width of the first resistive element.

19. The semiconductor device according to claim 12 , wherein, in the first resistive element, a region to be a depletion layer region in a diffusion region where the diffusion resistor is formed is changed by an applied voltage, and a width of a region that substantially functions as a resistor decreases when a high voltage is applied.

20. The semiconductor device according to claim 12 , wherein the ESD protection element includes a MOS transistor of which a gate, a source, and a back gate are connected to a ground, and a drain is connected between the power source terminal and the first resistive element.

21. A recording device comprising:
a recording head unit having discharge nozzles and a recording head substrate; and
an ink tank attached to the recording head unit,
wherein the recording head substrate comprises:
discharge elements each of which corresponds to a different one of the discharge nozzles;
a control circuit electrically connected to the discharge elements; and
the semiconductor device according to claim 12 electrically connected to the control circuit.

22. A semiconductor device comprising:
an anti-fuse element;
a transistor of which either one of a source and a drain is connected to one terminal of the anti-fuse element and the other one of the source and the drain is supplied with a first potential;
a first resistive element of which one terminal is connected to the other terminal of the anti-fuse element and the other terminal is connected to a power source terminal supplied with a second potential different from the first potential; and
an ESD protection element connected to an electric path between t

Assignees

• Canon Kk

Inventors

• Fujii Kazunari
• Negishi Toshio

Classifications

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• B41J2202/13

  Heads having an integrated circuit · CPC title

• B41J2/04543

  Block driving · CPC title

• B41J2/0458

  controlling heads based on heating elements forming bubbles · CPC title