Ramp signal generator, and CMOS image sensor using the same

Patent metadata

Field	Value
Publication number	US-9894309-B2
Application number	US-201615202339-A
Country	US
Kind code	B2
Filing date	Jul 5, 2016
Priority date	Dec 30, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A ramp signal generator may include a reference current generation unit suitable for generating a reference current based on a gain; a ramp signal generation unit suitable for generating a ramp signal according to the reference current; a replica current supply unit suitable for supplying a replica current using the reference current generation unit; and an offset compensation unit suitable for compensating for an offset of the ramp signal generated by the ramp signal generation unit using the replica current.

First claim

What is claimed is:

1. A ramp signal generator comprising:
a reference current generation circuit suitable for generating a reference current based on a gain;
a ramp signal generation circuit suitable for generating a ramp signal according to the reference current;
a replica current supply circuit suitable for supplying a replica current using the reference current generation unit; and
an offset compensation circuit suitable for compensating for an offset of the ramp signal generated by the ramp signal generation unit using the replica current.

2. The ramp signal generator of claim 1 , wherein, when the reference current generation circuit generates the reference current from one or more current mirror paths selected from a plurality of current mirror paths, the replica current supply circuit generates the replica current from remaining current mirror paths not selected by the reference current generation unit.

3. The ramp signal generator of claim 2 , wherein the replica current supply circuit comprises a plurality of switches suitable for selecting the remaining current mirror paths.

4. The ramp signal generator of claim 2 , wherein the replica current is derived by aggregating currents from one or more current mirror paths of the remaining current mirror paths.

5. The ramp signal generator of claim 2 , wherein the replica current supply circuit further comprises a separate current mirror path used to generate the replica current only.

6. The ramp signal generator of claim 4 , wherein the separate mirror current path is passed or interrupted by switching on or switching off a switch placed in the separate mirror current path.

7. The ramp signal generator of claim 6 , wherein the replica current is derived by aggregating currents from one or more current mirror paths of the remaining current mirror paths and a current from the separate current mirror path.

8. The ramp signal generator of claim 1 , wherein the replica current supply circuit generates the replica current according to an offset compensation ratio which is preset relative with the reference current from the current mirror paths selected by the reference current generation circuit.

9. A CMOS image sensor (CIS) comprising:
a pixel array suitable for outputting a pixel signal corresponding to incident light;
a row decoder suitable for selecting and controlling pixels within the pixel array for each row line according to a control of a control circuit;
a ramp signal generator suitable for generating a ramp signal according to the control of the control circuit, and compensating for the generated ramp signal by supplying a replica current to its output terminal;
a comparison circuit suitable for comparing pixel signals outputted from the pixel array to the ramp signal outputted from the ramp signal generator;
a counting circuit suitable for counting a clock applied from the control unit according to output signals from the comparison circuit;
a memory circuit suitable for storing counting information applied from the counting circuit under the control of the control unit; and
a column readout circuit suitable for outputting data of the memory circuit under the control of the control circuit,
wherein the ramp signal generator comprises a plurality of current mirror paths for supplying currents to be used to generate the ramp signal, and the replica current is derived from the plurality of current mirror paths.

10. The CIS of claim 9 , wherein the ramp signal generator comprises:
a reference current generation circuit suitable for generating a reference current based on a gain from the plurality of current mirror paths;
a ramp signal generation circuit suitable for generating the ramp signal according to the reference current from the reference current generation circuit;
a replica current supply circuit suitable for supplying the replica current using the plurality of current mirror paths; and
an offset compensation circuit suitable for compensating for an offset of the ramp signal generated through the ramp signal generation circuit using the replica current from the replica current supply circuit.

11. The CIS of claim 10 , wherein when the reference current generation circuit generates the reference current from one or more current mirror paths selected from the plurality of current mirror paths, the replica current supply circuit generates the replica current from remaining current mirror paths not selected by the reference current generation circuit.

12. The CIS of claim 11 , wherein the replica current supply circuit comprises a plurality of switches suitable for selecting the remaining current mirror paths.

13. The ramp signal generator of claim 11 , wherein the replica current is derived by aggregating currents from one or more current mirror paths of the remaining current mirror paths.

14. The ramp signal generator of claim 11 , wherein the replica current supply circuit further comprises a separate current mirror path used to generate the replica current only.

15. The ramp signal generator of claim 14 , wherein the separate mirror current path is passed or interrupted by switching on or switching off a switch placed in the separate mirror current path.

16. The ramp signal generator of claim 14 , wherein the replica current is derived by aggregating currents from one or more current mirror paths of the remaining current mirror paths and a current from the separate current mirror path.

17. The CIS of claim 10 , wherein the replica current supply circuit generates the replica current according to an offset compensation ratio which is preset relative with the reference current from the current mirror paths selected by the reference current generation circuit.

Assignees

• Sk Hynix Inc

Inventors

• Yun Gun Hee

Classifications

• G05F3/262 Primary

  using field-effect transistors only · CPC title

• H04N25/616

  involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title

• H03K4/026 Primary

  using digital techniques · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H03K4/48

  using as active elements semiconductor devices (H03K4/787 - H03K4/84 take precedence) · CPC title