CMOS image sensors with photogate structures and sensing transistors, operation methods thereof, and image processing systems including the same

Patent metadata

Field	Value
Publication number	US-9894301-B2
Application number	US-201514877539-A
Country	US
Kind code	B2
Filing date	Oct 7, 2015
Priority date	Oct 12, 2012
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

ACMOS image sensor includes a pixel array having a plurality of pixels. Each of the plurality of pixels includes: a photogate structure configured to be controlled based on a first gate voltage; and a sensing transistor including a charge pocket region formed in a substrate region, the sensing transistor being configured to be controlled based on a second gate voltage. Based on the first gate voltage, the photogate structure is configured to integrate charges generated in response to light incident on the substrate region. The sensing transistor is configured to adjust at least one of a threshold voltage of the sensing transistor and a current flow in the sensing transistor according to charges transferred from the photogate structure to the charge pocket region based on a difference between the first gate voltage and the second gate voltage.

First claim

What is claimed is:

1. A complementary-metal-oxide-semiconductor (CMOS) image sensor comprising:
a pixel array having a plurality of pixels, each of the plurality of pixels including,
a photogate structure configured to be controlled based on a first gate voltage, and
a sensing transistor including a charge pocket region formed in a substrate region, the sensing transistor being configured to be controlled based on a second gate voltage, wherein
based on the first gate voltage, the photogate structure is configured to integrate charges generated in response to light incident on the substrate region, and
the sensing transistor is configured to adjust at least one of a threshold voltage of the sensing transistor and a current flow in the sensing transistor according to charges transferred from the photogate structure to the charge pocket region based on a difference between the first gate voltage and the second gate voltage.

2. The CMOS image sensor of claim 1 , further comprising:
a readout circuit; wherein
the photogate structure includes a photogate transistor having a drain and a source in the substrate region,
the photogate transistor is configured to output a pixel signal corresponding to at least one of the adjusted threshold voltage and the adjusted current flow, and
the readout circuit is configured to output a digital image signal based on the pixel signal.

3. The CMOS image sensor of claim 2 , wherein the photogate transistor and the sensing transistor share one of the drain and the source, and wherein the photogate transistor and the sensing transistor are embodied in a planar structure.

4. The CMOS image sensor of claim 2 , wherein the photogate transistor and the sensing transistor are embodied in a vertical structure and share one of the drain and the source.

5. The CMOS image sensor of claim 1 , further comprising:
a readout circuit; wherein
the sensing transistor is configured to output a pixel signal corresponding to at least one of the adjusted threshold voltage and the adjusted current flow, and
the readout circuit is configured to output a digital image signal based on the pixel signal.

6. The CMOS image sensor of claim 1 , wherein the photogate structure and the sensing transistor are arranged in parallel.

7. The CMOS image sensor of claim 1 , wherein the photogate structure includes a photodiode in the substrate region.

8. The CMOS image sensor of claim 1 , wherein each pixel further includes a reset electrode configured to reset the pixel.

9. The CMOS image sensor of claim 1 , wherein:
the photogate structure includes,
a first gate electrode configured to receive the first gate voltage,
a first region in the substrate region, the first region being configured to output a pixel signal corresponding to at least one of the adjusted threshold voltage and the adjusted current flow, and
a shared region in the substrate region, the photogate structure and the sensing transistor sharing the shared region; and

the sensing transistor includes,
a second gate electrode configured to receive the second gate voltage, and
a second region in the substrate region, the charge pocket region being under the second gate electrode between the shared region and the second region.

10. The CMOS image sensor of claim 9 , wherein the sensing transistor further includes a channel region on or over the charge pocket region in the substrate region.

11. The CMOS image sensor of claim 1 , wherein:
the photogate structure includes,
a first gate electrode configured to receive the first gate voltage,
a first region in the substrate region, the first region being configured to output a pixel signal corresponding to at least one of the adjusted threshold voltage and the adjusted current flow, and
a shared region partially in the substrate region, the photogate structure and the sensing transistor sharing the shared region; and

the sensing transistor includes,
a second gate electrode configured to receive the second gate voltage, and
a second region over the shared region, the charge pocket region being between the shared region and the second region.

12. The CMOS image sensor of claim 1 , wherein:
the photogate structure includes,
a first gate electrode configured to receive the first gate voltage,
a first region on the substrate region, the first region being configured to output a pixel signal corresponding to at least one of the adjusted threshold voltage and the adjusted current flow, and
a shared region partially in the substrate region, the photogate structure and the sensing transistor sharing the shared region; and

the sensing transistor includes,
a second gate electrode configured to receive the second gate voltage, and
a second region over the shared region, the charge pocket region being between the shared region and the second region.

13. The CMOS image sensor of claim 1 , wherein:
the photogate structure includes,
a first gate electrode on the substrate region, the first gate electrode being configured to receive the first gate voltage; and

the sensing transistor includes,
a second gate electrode configured to receive the second gate voltage,
a first region in the substrate region, the first region being configured to output a pixel signal corresponding to at least one of the adjusted threshold voltage and the adjusted current flow, and
a second region in the substrate region, the charge pocket region being under the second gate electrode and between the first region and the second region.

14. The CMOS image sensor of claim 13 , wherein the photogate structure further includes a photodiode under the first gate electrode in the substrate region.

15. The CMOS image sensor of claim 1 , wherein each pixel further includes a reset region in the substrate region, the reset region being connected to a reset electrode configured to reset the pixel.

16. The CMOS image sensor of claim 1 , further comprising:
a row driver configured to,
set the first gate voltage to one of a ground voltage and a negative voltage, and
set the second gate voltage to the ground voltage to integrate the charges.

17. The CMOS image sensor of claim 1 , wherein the first gate voltage is greater than the second gate voltage, and wherein the CMOS image sensor further includes,
a row driver configured to supply the first gate voltage to transfer the charges from the photogate structure to the charge pocket region.

18. The CMOS image sensor of claim 1 , wherein the second gate voltage is greater than or equal to the first gate voltage, and the CMOS image sensor further includes,
a row driver configured to supply the second gate voltage, wherein
the photogate structure includes a photogate transistor having a drain and a source in the substrate region, and
the photogate transistor is configured to output a pixel signal corresponding to at least one of the adjusted threshold voltage and the adjusted current flow through one of the drain and the source.

19. The CMOS image sensor of claim 1 , wherein the second gate voltage is less than or equal to the first gate voltage, and wherein the CMOS image sensor further includes,
a row driver configured to supply the second gate voltage, wherein
the sensing transistor is configured to output a pixel signal corresponding to at least one of the adjusted threshold voltage and the adjusted current flow.

20. An image processing system comprising:
a CMOS image sensor including a pixel array having a plurality of pixels; and
a pr

Assignees

• Jin Young Gu
• Kim Min Ho
• Kim Tae Chan
• Min Dong Ki
• Sul Sang Chul
• Oh Tae Seok
• Lee Kwang Hyun
• Lee Tae Yon
• Jung Ju Hwan
• Samsung Electronics Co Ltd

Inventors

• Jin Young Gu
• Kim Min Ho
• Kim Tae Chan
• Min Dong Ki
• Sul Sang Chul
• Oh Tae Seok
• Lee Kwang Hyun
• Lee Tae Yon
• Jung Ju Hwan

Classifications

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/65 Primary

  applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/767

  Horizontal readout lines, multiplexers or registers · CPC title

• H01L27/14643

  Electricity · mapped topic