Phase continuity technique for frequency synthesis

Patent metadata

Field	Value
Publication number	US-9893875-B2
Application number	US-201615270444-A
Country	US
Kind code	B2
Filing date	Sep 20, 2016
Priority date	May 23, 2016
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.

First claim

What is claimed is:

1. A method of wireless communication, comprising:
powering down a first phase lock loop during a transmit subframe in time division duplex (TDD) communications;
clocking at least a portion of a delta sigma modulator with a reference clock for the first phase lock loop when the first phase lock loop powers down; and
maintaining phase continuity when the first phase lock loop turns back on.

2. The method of claim 1 , in which the first phase lock loop is a fractional-N phase lock loop.

3. The method of claim 1 , in which clocking at least a portion of the delta sigma modulator comprises clocking all of the delta sigma modulator or clocking only a portion of the delta sigma modulator.

4. A method of wireless communication, comprising:
changing a frequency of a phase lock loop from a first frequency to a second frequency;
switching between a first delta sigma modulator and a second delta sigma modulator when the frequency of the phase lock loop changes, while maintaining power on both the first delta sigma modulator and a clock of the first delta sigma modulator; and
maintaining phase continuity when the phase lock loop returns to the first frequency.

5. The method of claim 4 , in which the changing occurs when transitioning to a transmit subframe in time division duplex (TDD) communications.

6. The method of claim 4 , in which the first delta sigma modulator comprises a receive delta sigma modulator and the first frequency comprises a receive frequency.

7. The method of claim 4 , in which the second delta sigma modulator comprises a transmit delta sigma modulator and the second frequency comprises a transmit frequency.

8. The method of claim 4 , in which the first delta sigma modulator is assigned to the first frequency and the second delta sigma modulator is assigned to the second frequency to maintain a phase of the first frequency and the second frequency.

9. The method of claim 4 , further comprising assigning only a single delta sigma modulator and allocating an accumulator within the single delta sigma modulator that tracks a difference between receive (Rx) and transmit (Tx) frequencies.

10. An apparatus comprising:
a first phase lock loop including a delta sigma modulator;
a second phase lock loop, the first phase lock loop and the second phase lock loop associated with frequency division duplex (FDD) communications;
a control unit coupled to the first phase lock loop, the control unit configured to cause the first phase lock loop to power down; and
a reference clock device coupled to the delta sigma modulator, the reference clock device configured to generate a reference clock signal to clock at least a portion of the delta sigma modulator with the reference clock signal when the first phase lock loop powers down, the control unit configured to maintain phase continuity when the first phase lock loop turns back on based at least in part on the clocking, in which the control unit causes the first phase lock loop to power down during sleep mode while the delta sigma modulator and the reference clock of the first phase lock loop stay active to maintain phase continuity.

11. The apparatus of claim 10 , in which the first phase lock loop is a fractional-N phase lock loop.

12. The apparatus of claim 10 , in which the reference clock device generates a reference clock signal to clock all of the delta sigma modulator or only a portion of the delta sigma modulator.

13. An apparatus comprising:
a control unit coupled to a phase lock loop;
a first delta sigma modulator coupled to the phase lock loop; and
a second delta sigma modulator coupled to the phase lock loop, the control unit configured to change a frequency of the phase lock loop from a first frequency to a second frequency, the control unit configured to cause a switch between the first delta sigma modulator and the second delta sigma modulator when the frequency of the phase lock loop changes, while maintaining power on both the first delta sigma modulator and a clock of the first delta sigma modulator, the control unit configured to maintain phase continuity when the phase lock loop returns to the first frequency based at least in part on the maintaining of the power on both the first delta sigma modulator and the clock of the first delta sigma modulator.

14. The apparatus of claim 13 , in which the control unit is configured to change the frequency of the phase lock loop when transitioning to a transmit subframe in time division duplex (TDD) communications.

15. The apparatus of claim 13 , in which the first delta sigma modulator comprises a receive delta sigma modulator and the first frequency comprises a receive frequency.

16. The apparatus of claim 13 , in which the second delta sigma modulator comprises a transmit delta sigma modulator and the second frequency comprises a transmit frequency.

17. The apparatus of claim 13 , further comprising an accumulator within an assigned one of the first delta sigma modulator or the second delta sigma modulator, the accumulator configured to track a difference between receive (Rx) and transmit (Tx) frequencies.

Assignees

• Qualcomm Inc

Inventors

• Zanuso Marco
• Elbadry Mohammad
• HUNG Tsai Pi
• Sridhara Ravi
• Gatta Francesco
• Zhuang Jingcheng

Classifications

• H04L69/28

  Timers or timing mechanisms used in protocols · CPC title

• H04L7/033 Primary

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03L7/143

  by switching the reference signal of the phase-locked loop · CPC title

• H03L7/14 Primary

  for assuring constant frequency when supply or correction voltages fail · CPC title

• H04W84/042

  Public Land Mobile systems, e.g. cellular systems · CPC title