Isolated output switching circuit

Patent metadata

Field	Value
Publication number	US-9893724-B2
Application number	US-201615180775-A
Country	US
Kind code	B2
Filing date	Jun 13, 2016
Priority date	Jul 31, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A semiconductor device includes an output switching device having an input node, an output node, and a control input node. The control input node enables an input voltage applied to the input node to be switched to the output node. A gate pull-down circuit controls the control input node of the output switching device in response to at least one control signal. The gate pull-down circuit activates the output switching device by raising the voltage level of the control input node above the voltage level of the output node and deactivates the output switching device by clamping the control input node to the voltage level of the output node. A gate pull-up circuit receives an enable signal and generates the at least one control signal to the gate pull-down circuit in response to the enable signal.

First claim

What is claimed is:

1. A semiconductor device comprising:
an output switching device having an input node, an output node, and a control input node, the control input node enables an input voltage applied to the input node to be switched to the output node;
a gate pull-down circuit to control the control input node of the output switching device in response to at least one control signal, the gate pull-down circuit activates the output switching device by raising the voltage level of the control input node above the voltage level of the output node and deactivates the output switching device by clamping the control input node to the voltage level of the output node; and
a gate pull-up circuit that receives an enable signal and generates the at least one control signal to the gate pull-down circuit in response to the enable signal.

2. The semiconductor device of claim 1 , wherein the gate pull-down circuit includes at least one transistor device to apply a voltage to the control input node to activate and deactivate the output switching device.

3. The semiconductor device of claim 2 , wherein the gate pull-up circuit further comprises a slope control circuit to control a slope of the rise and fall time of the at least one control signal such that a breakdown voltage of the at least one transistor device is below a predetermined threshold.

4. The semiconductor device of claim 3 , wherein the slope control circuit includes at least a resistor and capacitor filter to control the rise and fall time of the at least one control signal and the breakdown voltage relates to a voltage between a gate and drain of the at least one transistor device or relates to a voltage between the gate and a body diode connection to the at least one transistor device.

5. The semiconductor device of claim 4 , wherein the at least one transistor device is delayed from turning off by the response of the resistor and capacitor filter in the slope control circuit to allow an inductive load connected to the output node to discharge during deactivation of the output switching device.

6. The semiconductor device of claim 5 , the gate pull-down circuit further comprising:
a series of coupled transistor devices that receive a bias current from the gate pull-up circuit to provide a bias voltage to a control input of the at least one transistor device; and
a bias that receives a voltage from the series of coupled transistor devices, the bias circuit includes a current mirror to enable a predetermined minimum bias current to flow though the at least one transistor device when the output switching device is activated and provide a predetermined pull-down current to the at least one transistor device when the output switching device is deactivated.

7. The semiconductor device of claim 6 , wherein each transistor device in the gate pull-down circuit is fabricated on an P type well (SPWELL) area of a semiconductor, the SPWELL area formed within an isolation epitaxial (EPI) region that is formed between an N type well (NWELL) ring, the isolation EPI region and the NWELL ring form an isolation diode to provide voltage isolation to an adjacent switching channel.

8. The semiconductor device of claim 7 , wherein a distance between the SPWELL area and the NWELL ring is controlled to a predetermined distance to provide a predetermined isolation voltage range to the adjacent switching channel.

9. The semiconductor device of claim 6 , wherein the gate pull-up circuit further comprises:
a first current source coupled to a voltage source to drive the series of coupled transistor devices, the first current source is switched in response to the enable signal to supply the bias current to the series of coupled transistor devices;
a second current source coupled to the voltage source to drive the bias circuit, the second current source is switched in response to the enable signal to supply pull-down current to the bias circuit when the output switching device is deactivated; and
a third current source coupled to the voltage source to drive the at least one transistor device in the gate-pull-down circuit, the third current source is switched in response to the enable signal to supply pull-up current to the at least one transistor device when the output switching device is activated.

10. The semiconductor device of claim 9 , further comprising a set of isolation transistor devices connected to the first, second, and third current source to pass current from the respective current sources in the gate pull-up circuits to the gate pull-down circuit.

11. The semiconductor device of claim 1 , further comprising at least one other gate pull-down circuit and at least one other gate pull-up circuit coupled to activate and deactivate at least one other output switching device.

12. The semiconductor device of claim 1 , wherein the output switching device comprises a bipolar junction transistor or a field effect transistor.

13. A semiconductor device comprising:
an output switching device having an input node, an output node, and a control input node, the control input node enables an input voltage applied to the input node to be switched to the output node;
a gate pull-down circuit to control the control input node of the output switching device in response to at least one control signal, the gate pull-down circuit includes at least one transistor device to apply a voltage to the control input node to activate and deactivate the output switching device;
a gate pull-up circuit that receives an enable signal and generates the at least one control signal to the gate pull-down circuit in response to the enable signal; and
the gate pull-up circuit comprising a slope control circuit to control a slope of the rise and fall time of the at least one control signal such that a breakdown voltage of the at least one transistor device is below a predetermined threshold.

14. The semiconductor device of claim 13 , wherein the gate pull-down circuit activates the output switching device by raising the voltage level of the control input node above the voltage level of the output node and deactivates the output switching device by clamping the control input node to the voltage level of the output node.

15. The semiconductor device of claim 13 , wherein the slope control circuit includes a filter comprising at least a resistor and capacitor to control the rise and fall time of the at least one control signal and the breakdown voltage relates to a voltage between a gate and drain of the at least one transistor device or relates to a voltage between the gate and a body diode connection to the at least one transistor device.

16. The semiconductor device of claim 13 , the gate pull-down circuit further comprising:
a series of coupled transistor devices that receive a bias current from the gate pull-up circuit to provide a bias voltage to a control input of the at least one transistor device; and
a bias circuit that receives a voltage from the series of coupled transistor devices, the bias circuit includes a current mirror to enable a predetermined minimum bias current to flow though the at least one transistor device when the output switching device is activated and provide a predetermined pull-down current to the at least one transistor device when the output switching device is deactivated.

17. The semiconductor device of claim 16 , wherein each transistor device in the gate pull-down circuit is fabricated on an SPWELL area of a semiconductor, the SPWELL area formed within an isolation epitaxial (EPI) region that is formed between an NWELL ring, the isolation EPI

Assignees

• Texas Instruments Inc

Inventors

• Nguyen Tri C
• Rahman Md Abidur
• Baldwin David J

Classifications

• H03K17/162 Primary

  without feedback from the output circuit to the control circuit · CPC title

• H03K2017/066

  Maximizing the OFF-resistance instead of minimizing the ON-resistance · CPC title

• H03K5/08

  by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30) · CPC title

• H03K5/07

  by the use of resonant circuits · CPC title

• H03K17/284

  in field effect transistor switches · CPC title