Edge detectors and systems of analyzing signal characteristics including the same

Patent metadata

Field	Value
Publication number	US-9893721-B2
Application number	US-201615206384-A
Country	US
Kind code	B2
Filing date	Jul 11, 2016
Priority date	Oct 19, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

An edge detector includes a differential signal generator, a sense amplifier and a latch. The differential signal generator delays an input signal to generate a first differential signal and inverts the input signal to generate a second differential signal. The sense amplifier amplifies a difference between the first differential signal and the second differential signal to generate a first amplification signal and a second amplification signal at a first edge of a test clock signal and resets the first amplification signal and the second amplification signal at a second edge of the test clock signal. The latch generates an edge signal corresponding to edge information of the input signal in response to the first amplification signal and the second amplification signal.

First claim

What is claimed is:

1. An edge detector, comprising:
a differential signal generator configured to delay an input signal to generate a first differential signal and configured to invert the input signal to generate a second differential signal;
a sense amplifier configured to amplify a difference between the first differential signal and the second differential signal to generate a first amplification signal and a second amplification signal at a first edge of a test clock signal and configured to reset the first amplification signal and the second amplification signal at a second edge of the test clock signal; and
a latch configured to generate an edge signal corresponding to edge information of the input signal in response to the first amplification signal and the second amplification signal.

2. The edge detector of claim 1 , wherein the input signal is a periodic signal having a first period (P), and wherein the test dock signal has a second period corresponding to a sum of a third period and a fourth period, and
wherein the third period corresponds to N*P, the fourth period corresponds to M*P, N is a natural number and M is a rational number greater than zero and smaller than one.

3. The edge detector of claim 1 , wherein a duty cycle of the edge signal is substantially the same as a duty cycle of the input signal, and a jitter of the edge signal at an edge is substantially the same as a jitter of the input signal at a corresponding edge,
the differential signal generator is configured to delay the input signal by a first time to generate the first differential signal, and to invert the input signal for a second time to generate the second differential signal, and
the first time is substantially the same as the second time.

4. The edge detector of claim 1 , wherein the differential signal generator comprises:
a delay circuit configured to generate the first differential signal by delaying the input signal; and
an inverting circuit configured to generate the second differential signal by inverting the input signal.

5. The edge detector of claim 4 , wherein the delay circuit comprises a PMOS transistor and an NMOS transistor and the input signal is input to a first internal node of the delay circuit,
wherein the PMOS transistor has a source coupled to the first internal node, a gate for receiving a first offset voltage and a drain coupled to a second internal node of the delay circuit,
wherein the first differential signal is output at the second internal node,
wherein the NMOS transistor has a drain coupled to the first internal node, a gate for receiving a second offset voltage and a source coupled to the second internal node, and
wherein the delay circuit is configured to adjust a first propagation delay of the delay circuit in response to the first offset voltage and the second offset voltage such that the first propagation delay is substantially the same as a second propagation delay of the inverting circuit.

6. The edge detector of claim 4 , wherein the delay circuit comprises a first inverter and a second inverter,
the first inverter has an input terminal for receiving the input signal and an output terminal coupled to an input terminal of the second inverter,
the second inverter has an output terminal at which the first differential signal is output, and,
a sum of a first propagation delay of the first inverter and a second propagation delay of the second inverter is substantially the same as a propagation delay of the inverting circuit.

7. The edge detector of claim 6 , wherein the delay circuit is configured to adjust the first propagation delay in response to a first offset voltage and a second offset voltage.

8. The edge detector of claim 4 , wherein the delay circuit includes a first exclusive OR gate and
the first exclusive OR gate has a first input terminal for receiving a ground voltage, a second input terminal for receiving the input signal and an output terminal that outputs the first differential signal,
wherein the inverting circuit includes a second exclusive OR gate, and
the second exclusive OR gate has a first input terminal for receiving a power supply voltage, a second input terminal for receiving the input signal and an output terminal that outputs the second differential signal, and
wherein a propagation delay of the first exclusive OR gate is substantially the same as a propagation delay of the second exclusive OR gate.

9. The edge detector of claim 1 , wherein the sense amplifier comprises first through fourth PMOS transistors and first through sixth NMOS transistors,
the first PMOS transistor has a source coupled to a power supply voltage, a gate for receiving the test clock signal and a drain coupled to a first internal node of the sense amplifier that outputs the first amplification signal,
the second PMOS transistor has a source coupled to the power supply voltage, a gate coupled to a second internal node of the sense amplifier and a drain coupled to the first internal node,
the third PMOS transistor has a source coupled to the power supply voltage, a gate coupled to the first internal node and a drain coupled to the second internal node that outputs the second amplification signal,
the fourth PMOS transistor has a source coupled to the power supply voltage, a gate for receiving the test clock signal and a drain coupled to the second internal node,
the first NMOS transistor has a drain coupled to the first internal node, a gate coupled to the second internal node and a source coupled to a third internal node of the sense amplifier,
the second NMOS transistor has a drain coupled to the second internal node, a gate coupled to the first internal node and a source coupled to a fourth internal node of the sense amplifier,
the third NMOS transistor has a drain coupled to the third internal node, a gate for receiving the test clock signal and a source coupled to a fifth internal node of the sense amplifier,
the fourth NMOS transistor has a drain coupled to the fourth internal node, a gate for receiving the test clock signal and a source coupled to a sixth internal node of the sense amplifier,
the fifth NMOS transistor has a drain coupled to the fifth internal node, a gate for receiving the first differential signal and a source coupled to a ground voltage, and
the sixth NMOS transistor has a drain coupled to the sixth internal node, a gate for receiving the second differential signal and a source coupled to the ground voltage.

10. The edge detector of claim 1 , wherein the sense amplifier resets the first amplification signal and the second amplification signal to a power supply voltage at the second edge of the test clock signal.

11. The edge detector of claim 1 , wherein the latch includes an S-R latch.

12. The edge detector of claim 1 , wherein a PMOS transistor in the differential signal generator, the sense amplifier or the latch is located in a P-well region in a primitive cell, and
an NMOS transistor in the differential signal generator, the sense amplifier or the latch is located in an N sub-region in the primitive cell.

13. The edge detector of claim 1 , wherein the first edge of the test clock signal is a rising edge and the second edge of the test clock signal is a falling edge.

14. A system of analyzing a signal characteristic, the system comprising:
an integrated circuit including an edge detector configured to generate a second signal corresponding to edge information of a first signal in response to a clock signal; and
a processor configured to analyze a characteristic of the first signal in response to the second signal, wherein the edge detector compris

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Dong Seok
• Kim Woo Seok
• Park Jae Jin
• Lim Dong Hyuk
• Chung Dae Young

Classifications

• H04L7/0037

  Delay of clock signal · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H01L27/11803

  Electricity · mapped topic

• H03K5/1534 Primary

  Transition or edge detectors · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title